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研究生:曾意婷
研究生(外文):Yi-Ting Tseng
論文名稱:將雜訊整形概念運用於連續逼近暫存量化器之三角積分調變器
論文名稱(外文):Design of Low-Power Delta-Sigma Modulator with Embedded Noise-Shaping SAR Quantizer
指導教授:林宗賢林宗賢引用關係
口試委員:林永裕劉深淵李泰成黃柏鈞
口試日期:2015-07-30
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:75
中文關鍵詞:雜訊整形連續逼近暫存量化器
外文關鍵詞:noise-shapingSAR ADC
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本論文包含兩個作品,第一個作品是一個低功耗的連續時間三角積分調變器,主要由一個三階的迴路濾波器、一個被截掉兩位元的六位元量化器所構成;第二個作品是一個具有量化誤差整形效果的八位元量化器所構成。
第一個作品提出了一個把具雜訊整形效果的截除器內嵌於連續逼近暫存量化器的技巧。此位元截除方法可減少數位類比轉換器的數目且可減輕動態匹配電路設計的複雜度,但量化器和截除器之整體反應時間約略是連續逼近暫存量化器需要轉換四個位元的轉換時間。我們用台積電90奈米互補式金氧半製程來實現,經實驗結果得知,本作品在3.5 MHz頻寛下以及110 MHz的取樣頻率下可量到65 dB的訊號雜訊比,調變器的功耗是3.8 mW,整體系統的FoM是350 fJ/Conv.-Step。
第二個作品提出了一個具有量化誤差整形效果的類比數位轉換器,此轉換器貢獻一階雜訊整形效果。此方法有機會在僅使用一個放大器的條件下實現多階量化誤差整形的效果。這個作品在台積電90奈米互補式金氧半製程下實現,在電源供應為1.2 V、取樣頻率為50 MHz的情況下,經量測結果得知,本作品在3.2 MHz頻寛下可量到49.8 dB的訊號雜訊比,調變器的功耗是1.5 mW。


Two works are discussed in this thesis. The first work is a low-power continuous-time delta-sigma modulator, which consists of a 3rd-order feed-back and feed-forward combined loop filter structure, a 6-bit quantizer with 2 bits truncated by a truncator and embedded with a noise-shaping mechanism. The second work presents an 8-bit noise-shaped SAR ADC, which improves the resolution of the data converter.
A 6-bit, low-power continuous-time delta-sigma modulator (CTDSM) embedded with a noise-shaped and truncated SAR quantizer is proposed in the first work. The bit truncation reduces the number of feedback DAC cells and relaxes the implementation of DEM circuit. The truncation process is embedded in the SAR quantizer which will not degrade the operation frequency of the modulator. Implemented in a 90-nm CMOS process, the measured performance shows a peak SNDR of 65 dB over a signal bandwidth of 3.5 MHz with 110 MHz sampling frequency. This modulator consumes a total power of 3.8 mW, resulting in an FoM of 350 fJ/Conversion-Step.
In second work, a low-power 8-bit noise-shaped SAR ADC is discussed. The proposed ADC gives first-order noise-shaping to the modulator, resulting in an 8-bit 1st-order delta-sigma modulator. This method has the opportunity to extend to higher-order noise-shaping using only one operational amplifier with the help of finite impulse response (FIR) filter. This modulator was realized in a 90-nm CMOS process. Under a power supply of 1.2 V and a sampling frequency of 50 MHz, the measured performance shows a peak SNR and SNDR of 56 dB and 49.8 dB, respectively, over a signal bandwidth of 3.2 MHz. The modulator consumes a total power of 1.5 mW.


Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Chapter 2 Background on Delta-Sigma Modulators 5
2.1 A Brief Overview of Delta-Sigma Modulator 5
2.1.1 Sampling and Quantization 5
2.1.2 Oversampling 7
2.1.3 Noise-Shaped Delta-Sigma Modulator 9
2.2 Loop Filter Topologies for CTDSM 13
2.2.1 Feed-Forward loop topology for CTDSM 13
2.2.2 All Feedback loop topology for CTDSM 14
2.2.3 Combination of Feed-Forward and Feedback loop topology for CTDSM 15
2.3 Non-Ideal Effects in a Continuous-Time Delta-Sigma Modulator 16
2.3.1 Clock Jitter 17
2.3.2 Excess-Loop-Delay 18
2.3.3 Loop Filter Coefficient Variation 19
2.3.4 Nonlinearity of Multi-Bit Quantizer 20
2.4 Summary 24
Chapter 3 Design and Implementation of Continuous-Time Delta-Sigma Modulator with Noise-Shaping Truncated SAR Quantizer 25
3.1 Introduction of the Main Idea 25
3.2 Proposed Noise-Shaping Truncated SAR Quantizer 26
3.3 System Design 28
3.3.1 Synthesis of Continuous-Time Delta-Sigma Modulator (CTDSM) 30
3.3.2 Quantization Bit Number Selection for the Proposed CTDSM 31
3.4 Circuit Implementation 34
3.4.1 Continuous-Time Integrator and the Op-amp 34
3.4.2 Digital-to-Analog Converter (DAC) 37
3.4.3 Proposed Noise-Shaping Truncated SAR Quantizer 38
3.5 Simulation Results 41
3.6 Experimental Results 45
3.6.1 Test Setup 45
3.6.2 Measurement Results 47
Chapter 4 Design and Implementation of Noise-Shaping Successive Approximation Register Analog-to- Digital Converter 53
4.1 Introduction and Motivation 53
4.2 Proposed Noise-Shaping SAR 54
4.3 Circuit Implementations 56
4.3.1 Successive Approximation Register Analog-to-Digital Converter 56
4.3.2 Time Control of Proposed Noise-Shaping SAR ADC 57
4.4 Simulation Results 58
4.5 Experimental Results 60
4.5.1 Test Setup 60
4.5.2 Measurement Results 62
Chapter 5 Future Work and Conclusion 69
5.1 Future Work 69
5.2 Conclusion 71
Reference 73


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