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研究生:何冠霖
研究生(外文):Kuan-Lin Ho
論文名稱:全CMOS輔助單點溫度校正之低溫度飄移參考電壓設計
論文名稱(外文):Design of an All-CMOS Low-temperature-drift Voltage Reference with Assisted-one-temperature-point Trim
指導教授:林宗賢林宗賢引用關係
口試委員:林永裕李泰成劉深淵黃柏鈞
口試日期:2015-07-30
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:84
中文關鍵詞:參考電壓溫度補償輔助單點溫度校正
外文關鍵詞:Voltage referencetemperature compensationassisted-one-temperature-point (A-OTP) trim
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在一個積體電路系統中,往往需要參考電壓,以負責提供一個穩定的電壓值,而此電壓值理想上不隨著溫度、供應電壓及製程變異而改變;在類比電路的應用中,扮演著不可或缺的角色。
本論文中提出一個全CMOS輔助單點溫度校正的參考電壓,可在0.8伏特的電源供應下運作。傳統的參考電壓,是以BJT做為核心元件來實現;但一個BJT需佔去0.75伏特以上的跨壓;因此,在先進製程的供壓不斷降低的趨勢下,採用BJT的架構漸漸不適合做為電路實現的方式。而全CMOS的電路架構雖然可解決此問題,但由於MOS本身較差的溫度特性,往往需要更為複雜的校正技術,才能得到較低的溫度係數。在本論文中的架構中,直接對偏壓電流進行室溫校正,以穩定MOS的溫度特性;因此可以在全MOS的電路組態底下,以簡單的校正流程,即可得到低溫度飄移的輸出電壓。
此參考電壓以台積電40奈米的製程設計;電路可在0.8伏特的供壓下操作,面積為0.049 mm2。總量測樣本為8顆,量測溫度範圍為 -10 ˚C ~ 100 ˚C;而量測結果顯示:平均的溫度係數約為30 ppm/˚C,三個標準差的電壓飄移僅為0.14 %,低頻的電源拒絕比為 -48 dB,且供壓敏感度小於1.8 %/V。

Voltage reference (VR) is required in integrated circuits for providing a stable voltage, which is ideally immune to temperature, supply and process variations. It undoubtedly plays a crucial role in analog circuit applications.
This thesis proposes an all-CMOS voltage reference with assisted-one-temperature -point trim in a 40-nm CMOS technology that is functional from 0.8-V supply. Conventionally, BJT-based references are commonly used, but a BJT consumes at least 0.75V headroom. Thus, they are not suitable for advanced technologies because of supply scaling. Previously solutions include BJT-free designs, but they exhibit worse temperature characteristics, or complex trimming methodology is demanded to achieve a reasonable temperature coefficient (TC). In this work, one-temperature-point trim on bias makes MOS exhibit better temperature characteristics. Thus, an all-MOS circuit topology featuring low temperature drift can be achieved with simple trimming procedures.
The chip is fabricated in a TSMC 40-nm CMOS technology. It works down to a supply of 0.8 V and occupies 0.049 mm2. Total 8 samples was measured from -10˚C to 100 ˚C. Measurement results show that the average TC is about 30 ppm/˚C and 3σ spread is only 0.14 %. Also, PSR of -48 dB at a low frequency is attained, and line sensitivity (LS) is below 1.8 %/V.


Chapter 1 Introduction 1
1.1 Introduction to Voltage Reference 1
1.2 Motivation and Objective 2
1.3 Thesis Overview 4
Chapter 2 Fundamentals of Voltage Reference 5
2.1 Characterization of Voltage Reference 5
2.1.1 Temperature Coefficient (TC) 5
2.1.2 Line Sensitivity (LS) 7
2.1.3 Power Supply Rejection (PSR) 8
2.1.4 Spread and Inaccuracy 9
2.2 Conventional Bandgap Reference 10
2.2.1 Basic Operations 11
2.2.2 Circuit Implementation 13
2.2.3 Curvature Compensation 15
2.3 Prior Arts of CMOS Voltage Reference 17
2.4 Trimming 20
2.4.1 One-Temperature-Point (OTP) Trim 21
2.4.2 Two-Temperature-Point (TTP) Trim 21
2.4.3 Assisted-One-Temperature-Point (A-OTP) Trim 22
Chapter 3 Operating Principles of an All-CMOS Voltage Reference with Assisted-One-Point Trim 25
3.1 Design Challenges 25
3.1.1 Challenges in a MOSFET-Based Design 25
3.1.2 Challenges in an Advanced Process Node 27
3.2 Main Proposed Idea 31
3.3 Transistor Physics 33
3.3.1 Temperature Dependency of Threshold Voltage 33
3.3.2 Temperature Slope of Gate-Source Voltage 35
3.4 Concepts of Bias Trim at Room Temperature 36
3.5 Concepts of A-OTP Trim for Model Correction 39
Chapter 4 Circuit Implementations of an All-CMOS Voltage Reference with Assisted-One-Point Trim 43
4.1 Block Diagram 43
4.2 Bias Generator 44
4.2.1 Constant-Gm Topology 45
4.2.2 Symmetrically Matched Voltage-Current Mirror (SM CVM) Topology 48
4.3 CTAT/PTAT Voltages (CPVs) Generator 51
4.4 Startup Circuit 53
4.5 Voltage Combiner 54
4.5.1 Voltage Adder with V-I Converters 54
4.5.2 Voltage Adder with Regulated-Cascode V-I Converters 57
4.6 Output Buffers 64
Chapter 5 Measurement Result 67
5.1 Layout and Chip Photo 67
5.2 Measurement Settings 67
5.3 Printed Circuit Boards Design 69
5.4 Measurement Results 71
5.4.1 Thermal Measurements 71
5.4.2 Supply Sensitivity Measurements 73
5.5 Comparison 74
Chapter 6 Conclusions and Future Works 79
6.1 Conclusions 79
6.2 Future Works 79
References 81

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