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研究生:李家安
研究生(外文):Chia-An Lee
論文名稱:基於現場可程式邏輯閘陣列之高解析度與高面積效率延遲線之實現
論文名稱(外文):Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
指導教授:黃俊郎黃俊郎引用關係
指導教授(外文):Jiun-Lang Huang
口試委員:鄭國興洪浩喬黃炫倫
口試委員(外文):Kuo-Hsing ChengHao-Chiao HongXuan-Lun Huang
口試日期:2015-07-28
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:55
中文關鍵詞:可編輯延遲電路現場可程式邏輯閘陣列高面積效率高解析度
外文關鍵詞:programmable delay lineFPGAarea-efficienthigh resolution
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本論文提出一種能夠實作在現場可程式邏輯閘陣列 (FPGA) 之高面積效率與高解析度可編輯延遲電路結構,並且提出高面積效率的延遲元件,可使用這些延遲元件去組合成欲達成規格的可編輯延遲電路。相較於先前之研究,我們所提出的方法在面積效率上高五到二十五倍。然而,如果要量測全部的延遲值需要花太多時間,因此,為了節省量測時間,我們只量測部分的延遲值,用這些部分的延遲值去推測出全部的延遲值,並從當中選取我們想要的延遲值。我們使用實驗室虛擬儀器工程平台 (LabVIEW)開發程式去自動化量測延遲值,並且可以同時控制PXI FPGA Carrier與示波器。我們所開發出的可編輯延遲電路的結果,其解析度為50 ps、動態範圍為11.1 ns,功率消耗為1毫瓦特。

In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells to construct the desired programmable delay line. Compared to previous works, our method is 5 to 25 times more efficient in resource usage. However, it costs too much time to measure all delay values. To save time, we only measure partial delay values and use the proposed generation program to predict all delay values. Then, using the proposed selection program to select the desired delay values. To automatically measure delay values, we develop the LabVIEW program which can control the PXI FPGA Carrier and the oscilloscope at the same time. The measurement results show that the proposed programmable delay line achieves 50 ps resolution with 11.1 ns dynamic range. The power consumption is 1 mW.

口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES viii
LIST OF TABLES xi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Proposed Technique 3
1.3 Contributions 5
1.4 Thesis Organization 6
Chapter 2 Preliminaries 7
2.1 Xilinx FPGA 7
2.2 Programmable Delay Line 9
2.2.1 LUT-based Delay Lines 9
2.2.2 Carry-Chain-based Delay Lines 11
2.3 Previous Work 12
2.3.1 Subset Sum Delay Line (SSDL) 12
2.3.2 A High Resolution and High Accuracy FPGA Formatter Prototype 13
Chapter 3 Proposed Programmable Delay Line 15
3.1 Design Specification 15
3.2 Architecture 15
3.3 Generation and Selection Program 17
Chapter 4 Proposed Delay Cells 19
4.1 Objective 19
4.2 Base on LUT 20
4.3 Base on Slice 22
4.3.1 Slice-based Fine Delay Line (SF_DL) 22
4.3.2 Slice-based Coarse Delay Line (SC_DL) 24
4.3.3 Slice-based Multi-Range Delay Line (SM_DL) 26
4.4 Base on CLB 28
4.4.1 CLB-based Fine Delay Line (CF_DL) 28
4.4.2 CLB-based Coarse Delay Line (CC_DL) 31
4.4.3 CLB-based Multi-Range Delay Line (CM_DL) 33
4.4.4 CLB-based CARRY4 Delay Line (C4_DL) 36
4.5 Location Dependent Process Variation 38
4.6 Summary and Guideline 39
4.6.1 Summary 39
4.6.2 Guideline 40
Chapter 5 Experiment Results 42
5.1 Delay Line Architecture 42
5.2 Automatic Measurement Platform 44
5.2.1 Experiment Environment 44
5.2.2 Automatic Measurement 45
5.3 Measurement Results 48
5.3.1 Result 48
5.3.2 Further Challenge 49
5.3.3 Runtime Edge Placement 50
5.3.4 Compare with Previous Work 52
Chapter 6 Conclusion 53
REFERENCE 54



[1]Spartan-6 FPGA Configurable Logic Block, Xilinx, 2010.
[2]Y.-Y. Chen, J.-L. Huang, T. Kuo, “Implementation of programmable delay lines on off-the-shelf FPGAs,” in AUTOTESTCON, 2013, pp. 1-4.
[3]M. Majzoobi, F. Koushanfar, S. Devadas, “FPGA PUF using programmable delay lines,” in International Workshop on Information Forensics and Security, 2010, pp. 1-6.
[4]P.-C. Shu, “A High Resolution and High Accuracy FPGA Formatter Prototype,” M.S. thesis, Nation Taiwan University, Taipei, Taiwan, 2014.
[5]H. Menninga, C. Favi, E. Charbon, “A multi-channel, 10ps resolution, FPGA-based TDC with 300MS/s throughput for open-source PET applications,” in Nuclear Science Symposium and Medical Imaging Conference, 2011, pp. 1515-1522.
[6]K. Daehoon, C. Yong, L. Sangwon, “An improved method of FPGA-based TDC for time-of-flight PET,” in Nuclear Science Symposium and Medical Imaging Conference, 2013, pp. 1-3.
[7]Y.-H. Chen, “A high resolution FPGA-based merged delay line TDC with nonlinearity calibration,” in International Symposium on Circuits and Systems, 2013, pp. 2432-2435.
[8]C.-Y. Wang, Y.-Y. Chen, J.-L. Huang, X.-L. Huang, “FPGA-Based Subset Sum Delay Lines,” in Asian Test Symposium, 2014, pp. 287-291.
[9]Spartan-6 Libraries Guide for HDL Designs, Xilinx, 2009.
[10]Constraints Guide, Xilinx, 2012.
[11]A.R. Syed, “Automatic delay calibration method for multi-channel CMOS formatter,” in International Test Conference, 2004, pp. 577-586.
[12]J. Park, I. Lee, Y.-S. Park, S.-G. Kim, K. H. Ryu, D.-H. Jung, K. Jo, C. K. Lee, H. Yoon, S.-O. Jung, W.-Y. Choi, and S. Kang. “Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment,” in International SoC Design Conference, 2012, pp. 185-187.
[13]The Fundamentals of Digital Semiconductor Testing. Soft Test, 2013.
[14]J. Li, Z. Zheng, M. Liu, S. Wu, “Large Dynamic Range Accurate Digitally Programmable Delay Line with 250-ps Resolution,” in International Conference on Signal Processing, 2006.
[15]E. Bergeron, M. Feeley, J.P. David, “Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA,” in International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008, pp. 265-268.
[16]Agilent InfiniiVision 3000 X-Series Oscilloscopes programmer’s Guide, Agilent, 2013.


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