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研究生:江冠穎
研究生(外文):Kuan-Ying Chiang
論文名稱:針對鰭式場效電晶體電路內跨邏輯閘錯誤之錯誤模擬器以及測試向量產生器
論文名稱(外文):Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
指導教授:李建模
指導教授(外文):Chien-Mo Li
口試委員:江介宏潘正聖
口試委員(外文):Jie-Hong JiangCheng-Sheng Pan
口試日期:2015-06-23
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:48
中文關鍵詞:鰭式場效電晶體微小延遲缺陷測試向量產生器錯誤模擬
外文關鍵詞:FinFETSDDATPGfault simulation
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在先進製程中,鰭式場效電晶體已經成為最有效解決短通道效應的解決方案。然而,先前的研究顯示,在鰭式場效電晶體中,有些缺陷會造成額外的微小延遲,而這些缺陷無法輕易的被傳統測試圖騰偵測到。有時候,因為製程特性,鰭式場效電晶體電路中的缺陷會同時影響多個邏輯閘,我們稱之為跨邏輯閘缺陷。藉由累計電路上的額外延遲,能夠提升偵測到缺陷的機率。在此論文中,我們針對鰭式場效電晶體內部之跨邏輯閘缺陷,提出FAST錯誤模擬。此錯誤模擬是特別針對鰭斷路跨邏輯閘缺陷所設計。為了產出針對FAST錯誤模擬之測試向量,我們提出FAST測試向量產生器、錯誤模擬器以及測試向量選擇器。實驗結果顯示,我們的測試向量與商業用一次偵測測試向量比較,我們的測試圖騰在FAST涵蓋率上好29%,在FAST SDQL上好4%。

FinFET has become the most popular solution to overcome short channel effects in advanced technology. However, some research show that defect in FinFET causes extra small delay and the defect is difficult to detect by traditional test sets. Sometimes, defect in FinFET circuits may affect multiple gates due to fabrication process. We named it a cross-gate defect. By accumulating the extra delay induced by the cross-gate defect, we can detect the small delay defect more easily. In this thesis, we proposed a FAST fault model for small delay faults induced by cross-gate defects in FinFET circuits. This fault model is especially designed for fins open cross-gate defect. FAST ATPG, fault simulation, and test pattern selection are also presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL than those of commercial tool timing-unaware 1-detect pattern sets.

致謝 i
摘要 ii
Abstract iii
Table of Contents iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Proposed Technique 4
1.3 Contribution 5
1.4 Organization 6
Chapter 2 Background 7
2.1 Introduction to FinFET 7
2.1.1 Structure of FinFET 7
2.1.2 Fault Modeling for Defects on Fin 8
2.2 Automatic Test Pattern Generation (ATPG) 10
2.2.1 Physical-aware ATPG 10
2.2.2 Cell-aware ATPG 11
2.2.3 Timing-aware ATPG 12
2.3 Test Metrics for Small Delay Defect (SDD) 14
2.4 Graphic Processing Unit (GPU) 17
2.4.1 GPU Architecture 17
2.4.2 Past Research in GPU Fault Simulation 19
2.4.3 Past Research in GPU ATPG (SWK) 21
Chapter 3 Proposed Techniques 26
3.1 Overall Flow 26
3.2 FAST Fault Model 27
3.3 FAST Fault List Generation 28
3.3.1 GP Extraction 28
3.3.2 Transition Combination Enumeration 29
3.3.3 Untestable Faults Identification 30
3.4 FAST ATPG 33
3.5 FAST Fault Simulation and Test Selection 36
3.6 Test Metrics for FAST fault 38
3.6.1 FAST coverage 38
3.6.2 FAST SDQL 39
Chapter 4 Experimental Results 40
4.1 Benchmark Circuits Analysis 41
4.2 Comparison with Commercial Tool ATPG 42
Chapter 5 Conclusion and Future work 44
References 45


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