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研究生:江品全
研究生(外文):Ping-Chuan Chiang
論文名稱:每秒傳輸五百億位元以上的次世代乙太網路系統傳收晶片
論文名稱(外文):50+Gb/s Transceivers for Next Generation Ethernet Systems
指導教授:李致毅李致毅引用關係
口試委員:林宗賢盧信嘉郭建男陳巍仁施鴻源
口試日期:2015-03-25
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:124
中文關鍵詞:100Gb/s乙太網路資料與時脈回復電路雷射二極體驅動晶片收發晶片
外文關鍵詞:100Gb/s Ethernetclock and data recoverylaser diode drivertransceiver
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過去的數十年來,乙太網路的速度,自每秒百萬位元,成長至每秒數百或數千億位元的數量級。其中,核心網路的成長速度大約每一年半成長兩倍,其成長速度之快,甚至超越了伺服器的輸入與輸出端之成長速度(大約每兩年成長兩倍)。於設計上,次世代的100-Gb/s乙太網路系統晶片,將面臨到舊有網路系統中可忽略的、甚至是不存在的問題。本論文中的第一部分,將廣泛且深入的以電晶體層級描述100-Gb/s乙太網路系統晶片之設計,並且進行充足的理論分析。其中包含了四通道的雷射二極體驅動陣列,以及四通道的轉阻-限幅放大器陣列。除此之外,我們亦於此部分中探討光學元件之特性與其等效模型。
100-Gb/s乙太網路系統將很快的成為主流產品。然而,IEEE於2013年發起的400-Gb/s乙太網路系統,可能的架構為利用八個通道,其中每個通道傳輸50-Gb/s的二位元或者是四階脈衝調變後的資料形式。除了乙太網路,短距離之高速傳輸的應用,以及晶片與晶片間的傳輸系統亦有此相同趨勢。本論文的第二部分將提出一個高達56-Gb/s的四階脈衝調變收發晶片。其中於傳輸器的部分,我們不但實現了具有9-dB高頻補償的前饋式等化器,亦實現了具有100%可調範圍的線性度預失真補償機制,期以能補償當今電吸收調變雷射的非線性特性。
本論文的第三部分提出了50-Gb/s以上之資料與時脈回復電路之設計方法。於2014年以前,並沒有任何文獻提出可以用互補式金氧半導體製程實現50-Gb/s以上之資料與時脈回復電路的任何辦法。在此部分中,我們展示了一個應用於二位元資料形式,並且可將時脈資訊由輸入資料中萃取出來之創新技術。一個1:8的解多工器亦一併設計於此接收器中,以利測量誤碼率。

The ever-growing volume of Ethernet has pushed the backbone network data rate from Mb/s to tens or hundreds of Gb/s in past decades. The core network data rate in backbone averagely doubles every 1.5 years, which is even faster than the data rate improvement of server I/Os (2× every two years). The 100-Gb/s Ethernet (100GbE) must deal with several difficulties, which are less serious or do not exist at all in older standards. The first part of this thesis provides a broad and deep description of the 100GbE chipset in transistor level with theoretical analysis. It consists of a 4-lane laser-diode driver (LDD) array, and a 4-lane transimpedance amplifier/limiting amplifier (TIA/LA) array. Optical components are characterized and modeled as well.
Modern standards such as 100-Gb/s Ethernet (100GbE) will soon become mainstream products. However, in next generation’s 400-Gb/s Ethernet systems, we may need 8-lane data channels, and each of them delivers 50-Gb/s data in NRZ or PAM4 format. Short-distance applications such as backplane and chip-to-chip data links have similar approaches. The second part in this thesis illustrates the design of a 56-Gb/s PAM-4 transceiver. The TX adopts half-rate feed-forward equalizer (FFE) with pre-distortion driver to achieve 9-dB maximum boosting and 100% linearity control, which can compensate the non-linearity of modern electroabsorption-modulated laser (EML).
The third part in this thesis illustrates a CMOS CDR design shooting for NRZ data format with data rate beyond 50 Gb/s. Before 2014, no CMOS clock and data recovery (CDR) circuit has been proven at such a high data rate. In this part, we present a NRZ receiver incorporates a unique technique to extract clock from the ultra high-speed data stream and demultiplex it by a factor of 8. The design difficulty for individual blocks and the whole integrated system has been reported with explanation and discussion.


口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 3
Chapter 2 4×25Gb/s Optical Front-end for 100GbE 4
2.1 Overview of 100GbE System 5
2.1.1 High-Speed Optical Links 6
2.1.2 Vertical-Cavity Surface-Emitting Laser (VCSEL) 10
2.1.3 High-Speed Photo Detector (PD) 14
2.1.4 Link Budget: VCSEL+Fiber+PD 16
2.2 4×25Gb/s Laser Diode Driver Array 19
2.3 4×25Gb/s TIA/LA Array 24
2.3.1 Transimpedance Amplifier (TIA) 26
2.3.2 Continuous-Time Linear Equalizer (CTLE) 37
2.3.3 Single-ended to Differential Conversion 38
2.3.4 Power Detector and V/I Convertor 39
2.4 Experimental Results 42
2.5 Summary 49
Chapter 3 56-Gb/s PAM4 Transceiver for 400GbE 50
3.1 Overview of 400GbE System 50
3.2 Package and Channel Limitations 53
3.2.1 PCB Fundamentals 53
3.2.2 Microstrip line and Grounded Coplanar Waveguide 55
3.3 Architecture and Building Blocks 65
3.3.1 Wideband Amplifier 66
3.3.2 30-Gb/s D-flipflop 67
3.3.3 Output Combiner 72
3.3.4 28-GHz Frequency Synthesizer 76
3.3.5 PAM4 Receiver 79
3.4 Measurement Results 83
3.4.1 PAM4 Transmitter 83
3.4.2 PAM4 Receiver 85
3.5 Summary 89
Chapter 4 A 56-Gb/s CDR Circuit in 65nm CMOS 90
4.1 Introduction to linear CDR 92
4.2 Architecture and Building Blocks 95
4.2.1 VCO, Clock Buffer and Dividers 96
4.2.2 Data Divided-by-two Circuit and Phase Detector 103
4.2.3 Demultiplexer and Phase Interpolator 109
4.3 Measurement Results 112
4.4 Summary 115
Bibliography 116
Vita 124

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