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研究生:許齡芸
研究生(外文):Ling-Yun Hsu
論文名稱:高解析度之多通道式時序數位轉換器於現場可程式化邏輯閘陣列之實現
論文名稱(外文):Implementation of High-resolution Multi-channel Time-to-digital Converter in FPGA
指導教授:黃俊郎黃俊郎引用關係
口試委員:洪浩喬鄭國興黃炫倫
口試日期:2015-07-29
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:58
中文關鍵詞:時序數位轉換器多通道區間分割現場可程式化邏輯閘陣列
外文關鍵詞:time-to-digital convertermulti-channelsub-divisionFPGA
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由於高時效性以及易於重製的特性,現場可程式化邏輯閘陣列被廣泛運用於時序數位轉換器相關研究。這篇論文提出了一個可實現於現場可程式化邏輯閘陣列之高解析度多通道式時序數位轉換器架構。該架構主要概念為藉由不同通道之位移切割舊有時序刻度以達到解析度提升之目的。另一方面,時序數位轉換器之動態範圍亦可透過通道位移延伸。除了硬體架構外,校準程序對於時序數位轉換器亦為重要之過程。在這篇論文中,我們針對單觸發訊號或是連續訊號,提出區間合併演算法,有效的重置分割後之時序數位轉換器之區間值,並且達到高解析度與高準確度。我們將所提出的架構實現於Xilinx Spartan 6系列之開發版DE-0630-00,於非線性度(INL/DNL)低於0.5個最低有效位元之條件下,可達到40皮秒之解析度與5.05奈秒之動態範圍。該實現過程僅使用小於百分之一的邏輯元件及功耗65微瓦特。

FPGA-based TDC (Time-to-Digital Converter) provides a relatively low cost and flexible solution that incurs no non-recurring engineering and manufacturing delay. A high resolution FPGA-based multi-channel time-to-digital converter architecture is proposed in this thesis. In the proposed multi-channel TDC, a programmable latency is added before each TDC channel. This not only enhances ultra-wide bins sub-division between the channels, but also extends the measurement dynamic range with low area overhead. Calibration process with the proposed bin-merging algorithm is applied to re-arrange bin widths to achieve high accuracy for single-shot and repeatable events. The proposed TDC is realized on a Xilinx Spartan 6 development board DE-0630-00achievies. It achieves 40-ps resolution and 5.05-ns dynamic range with maximum INL/DNL less than 0.5 LSB. Furthermore, the proposed TDC consumes only 1% of FPGA logic elements (134 slices out of a total of 62,664 slices) and consumes 65 mW.

口試委員會審定書 #
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES viii
LIST OF TABLES xi
Chapter 1 Introduction 1
1.1 Proposed Multi-Channel TDC Architecture 2
1.2 Contribution 2
Chapter 2 Preliminaries 4
2.1 Time-to-Digital Converter Overview 4
2.1.1 Counter-Based TDC 4
2.1.2 Tapped Delay Line TDC 6
2.1.3 Vernier TDC 7
2.2 FPGA-Based TDC 9
2.3 Constraints of FPGA 11
2.4 Previous Work 14
2.4.1 Wave Union TDC 14
2.4.2 A Low Cost TDC Validation Technique 17
Chapter 3 Proposed Multi-Channel TDC Architecture 20
3.1 Multi-Channel TDC Architecture 20
3.1.1 Concept of Multi-Channel TDC 20
3.1.2 Multi-Channel TDC Architecture 21
3.1.3 Resolution Improvement and Dynamic Range Extension 22
3.1.4 Measurement and Calibration Flow 24
3.2 Calibration: Bin-Merging Algorithm 27
3.2.1 Concept of Bin-Merging Algorithm 28
3.2.2 Flow of Bin-Merging Algorithm 29
Chapter 4 Implementation of the Multi-Channel TDC 32
4.1 Implementation of TDC Channel 32
4.1.1 Delay Cell 34
4.1.2 Capture Cell 35
4.1.3 TDC Step Cell 36
4.2 Implementation of Programmable Delay Line 37
4.2.1 Fine Delay Line 38
4.2.2 Coarse Delay Line 40
4.3 Interface on host PC 41
Chapter 5 Experiment Result 43
5.1 Measurement Setup 43
5.2 Raw Bin Width Measurement 43
5.3 Single-Shot Event Measurement 45
5.3.1 Results after Ultra-Wide Bin Sub-Division 45
5.3.2 Results after Calibration with Bin-Merging Algorithm 47
5.3.3 Comparison 49
5.3.4 Stochastic Validation 50
5.4 Repeatable Event Measurement 51
5.4.1 Results after Ultra-Wide Bin Sub-Division and Dynamic Range Extension 52
5.4.2 Results after Calibration with Bin-Merging Algorithm 53
5.4.3 Comparison 55
5.5 Comparison with Previous Work 56
Chapter 6 Conclusion and Future Work 57
6.1 Conclusion 57
6.2 Future Work 57
Reference 58


[1]D.I. Porat, “Review of sub–nanosecond time–interval measurement”, IEEE Transaction on Nuclear Science, Vol. NS–20, No. 5, pp. 36–51, 1973.
[2]G. S. Jovanovi´c, M. K. Stojˇcev, “Vernier’s Delay Line Time–to–Digital Converter”, Scientific Publications of the State University of Novi Pazar Series A: Applied Mathematics, Informatics and mechanics, Vol. 1, pp. 11-20, 2009.
[3]J. Wu, Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay”, in IEEE Nuclear Science Symposium, pp.3440 – 3446, 2008.
[4]J. Kalisz, “Review of methods for time interval measurements with picosecond resolution”, Metrologia (Institute of Physics Publishing), pp.17-32, 2004.
[5]Hewlett-Packard, “Manual of a Hewlett-Packard 10811 crystal oven oscillator”.
[6]H. Menninga, C. Favi, M.W. Fishburn, E. Charbon Sr., “A Multi-Channel, 10-ps Resolution, FPGA-Based TDC with 300MS/s Throughput for Open-Source PET Applications”, in IEEE Nuclear Science Symposium, pp.1515-1522, 2011.
[7]Y. Y. Chen, J. L. Huang, T. Kuo, “Implementation of Programmable Delay Lines on Off-the-Shelf FPGAs”, in IEEE AUTOTESTCON, pp.1-4, 2013.
[8]Xilinx, “Spartan-6 FPGA Configurable Logic Block User Guide”, 2010.
[9]Xilinx, “Spartan-6 FPGA Configuration User Guide”, 2014.
[10]J. Qi, Z. Deng, H. Gong, Y. Liu, “A 20ps Resolution Wave Union FPGA TDC with On-Chip Real Time Correction”, in IEEE Nuclear Science Symposium, pp. 396–399, 2010.
[11]J. Wu, Y. Shi, D. Zhu, “A low-power Wave Union TDC implemented in FPGA”, in Topical Workshop On Electronics For Particle Physics, 2011.


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