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研究生:管挺貴
研究生(外文):Ting-Kuei Kuan
論文名稱:數位鎖相迴路之自動迴路增益最佳化
論文名稱(外文):Automatic Loop Gain Optimization for Digital Phase-Locked Loops
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
口試委員:吳介琮汪重光林宗賢陳巍仁李泰成黃柏鈞梁哲夫
口試委員(外文):Jieh-Tsorng WuChorng-Kuang WangTsung-Hsien LinWei-Zen ChenTai-Cheng LeePo-Chiun HuangChe-Fu Liang
口試日期:2015-06-30
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:91
中文關鍵詞:數位鎖相迴路鎖相迴路頻寬迴路增益最佳化時脈抖動雜訊自動校正製程變異電壓變異溫度變異多速率雜訊模型
外文關鍵詞:Digital Phase-Locked LoopPhase-Locked LoopBandwidthLoop GainOptimizationClock JitterNoiseAutomatic CalibrationProcess VariationVoltage VariationTemperature VariationPVT VariationsMulti-Rate Noise Model
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從1930年代開始,鎖相迴路已廣泛的應用於無線通信、遠程通信、電腦、和其他電子產品。特別的是,鎖相迴路可以用來產生精準的時脈來供給各式的應用,如時脈資料回復電路、微處理器、與無線傳輸器等。在設計鎖相迴路時,設計者總是會遇到幾個基本但卻非常重要的問題:「什麼樣的迴路增益可以讓鎖相迴路有最佳的時脈抖動?」和「是否有自動迴路增益最佳化的電路可以去自動最佳化時脈抖動,且同時抑制製程與環境變異所造成的影響?」然而,已經過了好幾年,自動迴路增益最佳化技術與理論到目前為止尚未被解開。
本論文提出了自動迴路增益最佳化技術之理論與實踐,突破此長久以來的障礙。數位鎖相迴路使用的相位偵測器區主要分為兩大類:一類是時間數位轉換器,而另一類是數位砰砰相位偵測器。該兩大類的數位鎖相迴路均會在本論文中探討。第一章,點出本論文的貢獻;第二章,在數位鎖相迴路(時間數位轉換器)上,實現自動迴路增益最佳化技術;第三章,在數位砰砰鎖相迴路上,實現自動迴路增益最佳化技術。除此之外,非線性數位砰砰相位偵測器的增益,在同時考慮了內部與外部的雜訊源(不同於傳統),其解析解被推導出來。並建立多速率的雜訊模型,來更深入探討鎖相迴路的週期性統計特性,揭露了尚未被討論過的特別現象。另外在台積電40奈米CMOS製程上,實做了一個使用自動迴路增益最佳化與迴路延遲減少技術的數位砰砰鎖相迴路。最後,在第四章作總結。


Since 1930s, phase-locked loops (PLLs) have been widely employed in radio, telecommunications, computers and other electronic devices. Specifically, they can be used to generate well-timed clocks for a variety of applications such as clock and data recovery (CDR), microprocessor clock generation, and wireline transmitters. In designing the PLLs, fundamental but quite important questions always arise: “What is the optimal loop gain for a PLL system to achieve the best jitter performance?” and “Can this optimal loop gain be automatically attained in background to tolerate process and environment variations?” Unfortunately, the theory of the automatic loop gain optimization technique has not been revealed so far.
This thesis presents the theory and the practice of the automatic loop gain optimization technique for digital PLLs (DPLLs) to breakthrough that traditional barrier. The DPLLs are often classified into two types with respect to their phase detector: a time-to-digital converter (TDC) or a bang-bang phase detector (BBPD), and this thesis will discuss both two types in two chapters. Chapter 1 highlights the contributions of this thesis to the world. Chapter 2 demonstrated the loop gain optimization technique for TDC-based DPLLs. Chapter 3 demonstrated the loop gain optimization technique for digital bang-bang PLLs (DBPLLs). In addition, the gain of the nonlinear BBPD is derived, taking into account the external and the internal noise sources simultaneously (different from the conventional approach). The multi-rate noise model is constructed to investigate the cyclostationary phenomenon of the PLLs, which reveals undisclosed secrets. A DBPLL using the automatic loop gain optimization and the loop latency reduction techniques is implemented. The chip was fabricated in TSMC 40nm CMOS Technology. Finally, the conclusion and the future work are drawn in Chapter 4.


1. Overview of Background and Contribution 1
1.1 Impact of the Loop Gain 2
1.2 Impact of the Loop Latency 2
1.3 Closed-Form Expression of the Gain of the Bang-Bang Phase Detector 3
1.4 Closed-Form Expression of the RMS Jitter 4
1.5 Loop Latency Reduction Technique 4
1.6 Automatic Loop Gain Optimization Technique 5
1.7 Multi-Rate Noise Model 5
1.8 Cyclostationary Phenomenon 6

2. An Automatic Loop Gain Optimization Technique for TDC-based DPLLs 7
2.1 Introduction 7
2.2 Noise Analysis of the DPLL 10
2.3 Automatic Loop Gain Optimization Technique 17
2.3.1 Information of the TDC Output 17
2.3.2 Automatic Loop Gain Control 33
2.3.3 Impact of Loop Latency 38
2.3.4 Stability 42
2.4 Simulation Results 44
2.5 Summary 55

3. A DBPLL with Automatic Loop Gain Control and Loop Latency Reduction 57
3.1 Introduction 57
3.2 Loop Latency Reduction of the DPLL 60
3.3 Noise analysis of the DBPLL 63
3.3.1 Analysis of the DBPLL using a Single-Rate Noise Model 63
3.3.2 Extension to a Multi-Rate Noise Model 65
3.4 Proposed DBPLL with Automatic Loop Gain Control 69
3.4.1 System Architecture 69
3.4.2 Intuitive Observation for Loop Gain Optimization 70
3.4.3 ALGC 72
3.4.4 Split-Control DCO 73
3.5 Measurement Results 74
3.6 Summary 79

4. Conclusion and Future Work 81
4.1 Conclusion 81
4.2 Future Work 82

Bibliography 83

Appendix 89
A1 Stability Criterion for the DPLL with Loop Latency 89


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