跳到主要內容

臺灣博碩士論文加值系統

(35.175.191.36) 您好!臺灣時間:2021/08/01 00:53
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:葉哲維
研究生(外文):Che-Wei Yeh
論文名稱:應用於小面積與背景校正供應電壓雜訊之鎖相迴路
論文名稱(外文):Applications of Phase-Locked Loops with Area-Efficiency and Background Supply Noise Cancellation
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
口試委員:林宗賢李泰成梁哲夫
口試委員(外文):Tsung-Hsien LinTai-Cheng LeeChe-Fu Liang
口試日期:2015-06-30
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:59
中文關鍵詞:鎖相迴路次諧波注入鎖定相位雜訊無除頻器供應電壓雜訊方均根抖動
外文關鍵詞:phase-locked loopsub-harmonically injection-lockedphase noisedivider-lesssupply-noisejitter
相關次數:
  • 被引用被引用:0
  • 點閱點閱:647
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
這篇論文的主題主要分為兩個部分,第一部分實現了一個具有小面積與無除頻器之次諧波注入鎖相迴路。次諧波注入鎖定的技巧被用來壓抑振盪器之相位雜訊。藉由降低迴路濾波器的電容值並同時確保次諧波注入鎖相迴路的穩定性,我們提出了一個小面積的次諧波注入鎖相迴路。除此之外,我們也提出了一個注入時間點校正之技巧去對齊振盪器之最佳注入點。量測到的相位雜訊驗證了次諧波注入鎖相迴路在無除頻器時,有較佳的雜訊效能,相較於有除頻器的情況。方均根抖動量為0.64ps,總面積為0.0074mm2.
第二部分實現了一個背景校正供應電壓雜訊的全數位鎖相迴路。我們使用了供應雜訊電流消去的做法來改善因為振盪器的供應電壓有雜訊存在所造成方均根抖動量變差的情況。我們提出了一個數位校正的方式去精準校正全數位鎖相迴路在不同製程、電壓、溫度引起的變異。在振盪器的供應電壓注入峰對峰值為50 mV,頻率為10 kHz的弦波雜訊時,量測到的峰對峰值抖動量從原本的41.87 ps降低至29.11 ps。量測到的方均根抖動量從原本的 4.43 ps 降低到 4.03 ps。經由供應電壓雜訊所引起的突波從原本的 -13.88 dB降低到 -25.41 dB。在未注入供應電壓雜訊時,量測到的峰對峰值和方均根抖動量分別為 29 ps 和 3.4ps。此全數位鎖相迴路的功耗和面積分別為2.915 mW 以及0.0216mm2.


This thesis consists of two parts. The first part implements an area-efficient divider-less sub-harmonically injection-locked PLL (SIPLL). Sub-harmonically injection-locked technique is employed to suppress VCO accumulation noise. Besides, an area-efficient SIPLL is present to reduce the capacitor in the loop filter, which also ensures the SIPLL to be stable. In addition, a self-adjusted injection timing method is also proposed. The measure phase noise validates the better performance without a divider compared with that with a divider. The RMS jitter is 0.64 ps. Moreover, the total area is 0.0074 mm2.

The second part implements a digital phase-locked loop (DPLL) with background supply noise cancellation. The DPLL employs supply noise current cancellation to mitigate jitter performance degradation due to supply noise on the oscillator supply voltage. A digital background cancellation is proposed to accurately cancel the supply noise under different process, and temperature conditions. In the presence of a 50 mVPP 10 kHz sinusoidal supply noise tone, the cancellation scheme reduces the peak-to-peak jitter from 41.87 ps to 29.11 ps. The rms jitter is reduced from 4.43 ps to 4.03 ps and the spurious supply noise spur is improved from -13.88 dB to -25.41 dB. In the absence of any supply noise, the peak-to-peak jitter and rms jitter are 29 ps and 3.4ps, respectively. The power consumption is 2.915mW and its active area is 0.0216mm2.


1. Introduction………………………………………………………… 1
1.1 Phase-Locked Loop…….……………………………………. 1
1.2 Low Phase Noise PLL……………………………………...... 3
1.3 Overview…………………………………………………….. 3
2. An Area-Efficient Divider-Less Sub-Harmonically Injection-Locked PLL…………………………………………………………………………………7
2.1 Design Principle………………………………7
2.2 System Architecture…………………………………10
2.2.1 System Description………………………10
2.2.2 Circuit Description………………………13
2.3 Linear Model Analysis ………………………………17
2.4 Simulation Result………………………………… 20
2.5 Experiment Result………………………………… 21
2.6 Performance Summary…………………………… 25
3. A 3.2 GHz Digital Phase-Locked Loop with Background Supply Noise Cancellation………………………………27
3.1 Supply Noise Cancellation…………………………27
3.2 DPLL Using Background Supply Noise Cancellation………………………………………………31
3.2.1 System Description…………… 31
3.2.2 Circuits Description……………………36
3.2.3 Analysis………………………………… 39
3.3 Simulation Result……………………………… 40
3.4 Experiment Result…………………………… 42
3.5 Performance Summary…………………… 53
4. Conclusion and Future Work………………………… 55
4.1 Conclusion…………………………………………………… 55
4.2 Future Work………………………………………………… 56
Bibliography ……………………………………………………………… 57




[1]C. F. Liang and K.J. Hsiao, “An Injection-Locked Ring PLL with Self-Aligned Injection Window,” in ISSCC Dig. Tech. Papers, pp. 90–91, Feb. 2011.

[2]W. Deng, D. Yang, T. Ueno, T. Sirburanon, S. Kondo, K. Okada, and A. Matsuzawa, “A 0.0066mm2 780μW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-Coupled Oscillator Using Edge-Injection Technique”, in ISSCC Dig. Tech. Papers, pp. 266-267, Feb. 2014.

[3]S. Ye, L. Jansson, and I. Galton, “A Multiple-Crystal Interface PLL with VCO Realignment to Reduce Phase Noise,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002.

[4]Y.C. Huang and S. I. Liu, “A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417–428, Feb. 2013.

[5]D. Park and S. Cho, “A 14.2mW 2.55-to-3GHz Cascaded PLL with Reference Injection, 800MHz Delta-Sigma Modulator and 255fsrms Integrated Jitter in 0.13µm CMOS,” in ISSCC Dig. Tech. Papers, pp. 344-345, Feb. 2012.

[6]I. T. Lee, Y. J. Chen, S. I. Liu, C. P. Jou, F. L. Hsueh, and H. H. Hsieh, “A Divider-Less Sub-Harmonically Injection-Locked PLL with Self-Adjusted Injection Timing,” in ISSCC Dig. Tech. Papers, pp. 414–415, Feb. 2013.

[7]W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, “A 0.022mm2 970μW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits,” in ISSCC Dig. Tech. Papers, pp. 248–249, Feb. 2013.

[8]P. Park, J. Park, H. Park, and S. Cho, “An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS,” in ISSCC Dig. Tech. Papers, pp. 336-337, Feb. 2012.

[9]M. Song, Y. H. Kwak, S. Ahn, H. Park, and C. Kim, “10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation,” IEEE Trans. on Very Large Scale Integr. Syst., vol. 21, no. 11, pp. 2080-2093, Nov. 2013.
PAPER II Start
[10]E. Alon, J. Kim, S. Pamarti, K Chang, and M. Horowitz, “Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006.

[11]T. Wu, K. Mayaram, and U. Moon, “An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007.

[12]S. Y. Kao and S. I. Liu, “A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 592-602, Apr. 2011.

[13]Y. C. Huang, C. F. Liang, H. S. Huang, and P. Y. Wang, “A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO,” in ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2014.

[14]A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration,” in ISSCC Dig. Tech. Papers, pp. 92-93, Feb. 2011.

[15]J. Liu, T. K. Jang, Y. Lee, J. Shin, S. Lee, T. Kim, J. Park, and H. Park, “A 0.012 mm2 3.1 mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider,” in ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2014.

[16]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Companies, Inc., 2002.

[17]J. Crossley, E. Naviasky, and E. Alon, “An Energy-Efficient Ring-Oscillator Digital PLL,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2010.

[18]T. Miki, Y. Nakamura, M. Nakaya, S. Asai,Y. Akasaka, and Y. Horiba, “An 80-MHz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 21, no. 6, pp. 983–988, Dec. 1986.

[19]T.-K. Jang, X. Nan, F. Liu, J. Shin, H. Ryu, J. Kim, T. Kim, J. Park, and H. Park, “A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter,” in ISSCC Dig. Tech. Papers, pp. 254-255, Feb. 2013.

[20]J.-P. Hong, S.-J. Kim, J. Liu, N. Xing, T.-K. Jang, J. Park, J. Kim, T. Kim, and H. Park, “A 0.004mm2 250μW ΔΣ TDC with Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications,” in ISSCC Dig. Tech. Papers, pp. 240-241, Feb. 2012.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關點閱論文