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研究生:葉尚榮
研究生(外文):Shang-Rong Ye
論文名稱:應用於電力線通訊系統之低功耗OOK收發器暨HomePlug AV高速接收器
論文名稱(外文):A Low-Power OOK Transceiver and HomePlug AV Receiver for Powerline Communication Applications
指導教授:陳中平陳中平引用關係
口試委員:陳巍仁李泰成曹恆偉林益勝
口試日期:2015-06-29
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:86
中文關鍵詞:二元振幅鍵控家用電力線網路聯盟收發器可變增益放大器管線式類比數位轉換器
外文關鍵詞:On-Off KeyingHomePlug AVTransceiverPGAPipelined ADC
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隨著科技的進步,網路通訊在我們生活中扮演著不可或缺的角色,所以通訊介面積體電路的設計也越來越重要,因此本論文針對電力線傳輸提出了一個使用OOK調變的低功耗且低成本收發器,以及HomePlug AV高速接收器;使用OOK調變技術收發器來實現電力線傳輸系統,可以降低功率損耗以及晶片面積,另一個則為符合HomePlug AV規格的高速接收器,內部包含了可變增益放大器以及管線式類比數位轉換器。
第一個晶片為使用On-Off Keying(OOK)調變技術的收發器,本次設計使用台積電0.25微米製程,在1.2 MHz載波頻率下可達到傳輸速率至45Kbps,操作於傳輸速率為10Kbps時的功率消耗為34mW,並且可以還原傳輸一公尺及五公尺後的數據。
第二個晶片為符合HomePlug AV的高速接收器,本次設計採用台積電90奈米製程,量測結果在取樣頻率為100MS/s時,輸入頻率50MHz下ENOB和SFDR為6.85和49.98dB,當時脈為120MS/s對於60MHz的輸入頻率時,ENOB和SFDR為6.55和53.88dB。在100MS/s的操作頻率之下,電路的消耗功率為73.2mW。


By the evolution of technology, digital data communication systems have become essential to our daily life. This dissertation proposes a low-power and low-cost On-Off Keying(OOK) transceiver for powerline communication (PLC) system and a receiver for HomePlug AV powerline communication system standard. The OOK modulation not only saves the power consumption but also saves the area cost. The HomePlug AV receiver includes a PGA and a pipelined ADC.
The OOK PLC transceiver was fabricated in TSMC 0.25um CMOS technology. With the 1.2 MHz carrier frequency, the transceiver achieves 45 Kbps data rate. When the transceiver operates at 10 Kbps data rate, the power consumption is 34mW. Moreover, the transceiver can recover the NRZ data by 1-meter and 5-meter powerline cable.
The receiver for HomePlug AV powerline communication was implemented in TSMC 90nm CMOS technology. When the receiver operate at 100MS/s sampling rate with 50MHz input frequency, the measured ENOB and SFDR is 6.85 and 49.98dB. In 120MS/s sampling rate with 60MHz input frequency, the measured ENOB is 6.55 and SFDR is 53.88dB respectively. The receiver consumes 73.2mW from 1.2-V supply when the sampling rate is 100MS/s.


口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES ix
LIST OF TABLES xiv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Power Line Communication 3
2.1 Broadband Power Line Communication 4
2.2 HomePlug 4
2.2.1 Usage [4] 5
2.2.2 Version of HomePlug Standard [4] 6
2.3 IEEE 1901 8
2.3.1 Description of IEEE 1901 [5][6] 8
2.4 Analog Front-end of PLC System 9
2.4.1 In-House Applications 9
2.4.2 The Challenge of Power Line Communications 10
2.4.3 Digital Communication System 11
2.4.4 Analog Front-end for Power Line Communication System 14
Chapter 3 Proposed OOK Transceiver 16
3.1 Introduction 16
3.2 The Design of Transmitter 17
3.2.1 OOK Modulator 18
3.2.2 Source Follower Buffer 20
3.2.3 Line Driver 22
3.3 The Design of Receiver 24
3.3.1 Programmable Gain Amplifier [1] 25
3.3.2 OOK Demodulator 29
3.4 Layout & Post-Layout Simulation 30
3.4.1 Layout 30
3.4.2 Post-Layout Simulation Results 31
3.4.3 Summary 37
3.5 Experimental Results 37
3.5.1 Measurement setup 37
3.5.2 PCB design and Die Photo 38
3.5.3 Measurement Result 41
3.6 Summary 44
Chapter 4 An Analog Front-end Receiver for Homeplug AV Powerline Communication in 90 nm CMOS 46
4.1 Introduction 46
4.2 Programmable Gain Amplifier 46
4.2.1 Receiver in PLC Analog Front-end 46
4.2.2 Attenuator 47
4.2.3 Gain cell 48
4.2.4 Programmable Gain Amplifier (PGA) 50
4.3 The 10-bit 200 MS/s Pipelined Analog-to -Digital Converter 52
4.3.1 Performance metrics[13] 52
4.3.2 The Architecture of Pipelined ADC 58
4.3.3 Building Blocks of Pipelined ADC and Design Consideration 59
4.4 Layout & Post-Layout Simulation 66
4.4.1 Layout 66
4.4.2 Post-Layout Simulation Results 67
4.5 Experimental Result 73
4.5.1 Measurement Environment setup 73
4.5.2 PCB layout and Die photo 75
4.5.3 Experimental Result 76
4.6 Summary 80
Chapter 5 Conclusion and Future Work 82
5.1 Conclusion 82
5.2 Future Work 83


[1]詹凱翔, “A High Dynamic Range, Low Gain Error Programmable Gain Amplifier
for Powerline Communication System,” Master Thesis, NTU, 2012.
[2]Spectrum Planning Team, Radiofrequency Planning Group, Australian Communications Authority, Broadband Powerline Communications Systems: A Background Brief, Sep. 2003. Retrieved from: https://docs.google.com/viewer?url=http://www.acma.gov.au/webwr/radcomm/frequency_planning/spps/0311spp.pdf&pli=1
[3]Halid Hrasnica, Abdelfatteh Haidine, and Ralf Lehnert, Broadband Powerline Communications Networks: Network Design, England, John Wiley & Sons Ltd, 2004.
[4]HomePlug. (n.d.). Retrieved March 19, 2012, from http://en.wikipedia.org/wiki/HomePlug
[5]IEEE Standard for Broadband over Power Line Networks: Medium Access Control and Physical Layer Specifications. IEEE Standards Association, Dec. 30, 2010.
[6]IEEE 1901 (n.d.). Retrieved March 6, 2012, from http://en.wikipedia.org/wiki/IEEE_1901
[7]Olivier Monnier, “TI Delivers Flexible Power Line communications Solutions,” White Paper, Texas Instruments, 2010.
[8]Amplitude-shift keying (n.d.). Retrieved May 12, 2015, from https://en.wikipedia.org/wiki/Amplitude-shift_keying
[9]Phase-shift keying (n.d.). Retrieved May 12, 2015, from https://en.wikipedia.org/?title=Phase-shift_keying
[10]Huy-Hieu Nguyen, Quoc-Hoang Duong, Huy Binh Le, Jeong-Seon Lee, and Sang-Gug Lee, “Low-power 42 dB-linear single-stage digitally-controlled variable gain amplifier,” Electronics Letters, Vol. 44, No. 13, pp. 780-782, Jun. 19, 2008.
[11]Huy-Hieu Nguyen, Hoai-Nam Nguyen, Jeong-Seon Lee, and Sang-Gug Lee, “A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier,” IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 56, No. 9, pp. 699-703, Sep. 2009.
[12]Keith Findlater, Toby Bailey, Adria Bofill, Neil Calder, Seyed Danesh, Robert Henderson, William Holland, Jed Hurwitz, Steve Maughan, Alasdair Sutherland, Ewan Watt, “A 90nm CMOS Dual-Channel Powerline Communication Analog Front End for Homeplug AV with a Gigabit extension,” IEEE International Solid-State Circuits Conference: Digest of Technical Papers, pp. 464-628, Feb. 2008.
[13]洪晟淵, “Design of Pipelined ADC for PowerLine Communication System,”
Master Thesis, NTU, 2013.
[14]S. H. Lewis, H. S. Fetterman, G. F. Griss Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," in IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
[15]Cho T.B. and Gray P.R., “A 10-b 20Msample/s 35mW pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
[16]Lewis S.H. and Gray P.R., “A pipelined 5-Msamples/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuit, vol. SC-22, no. 6, pp. 954-961, Dec. 1988.
[17]B. Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1995.
[18]D. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley & Sons, New York, 1997.
[19]T. Cho, “Low-power, low-voltage, analog-to-digital converter technique using pipelined architectures, “Ph. D. Thesis, University of California, Berkeley, 1995.
[20]Abo A.M. and Gray P.R., “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.


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