跳到主要內容

臺灣博碩士論文加值系統

(18.204.48.64) 您好!臺灣時間:2021/08/03 11:37
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:徐振凱
研究生(外文):Chen-Kai Hsu
論文名稱:一個單通道十位元四億赫茲導管式類比數位轉換器
論文名稱(外文):A Single-Channel 10-bit 400-MS/s Pipeline ADC
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
口試委員:劉深淵林宗賢陳信樹謝志成
口試委員(外文):Shen-Iuan LiuTsung-Hsien LinHsin-Shu ChenChih-Cheng Hsieh
口試日期:2015-04-10
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:68
中文關鍵詞:高速低功耗管線式類比數位轉換器
外文關鍵詞:High-speedlow-powerpipeline ADC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:152
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
類比數位轉換器是連接真實世界與離散運算領域的關鍵元件。
此篇論文提出了一個在九十奈米製程中實現的低功率管線式類比數位轉換器。然而放大器對於管線式類比數位轉換器來說,是一個非常重要且不可或缺的元件,另外為了使得管線式類比數位轉換器有良好的性能,放大器需要消耗相當可觀的功率消耗。管線式類比數位轉器使用n通道金氧半場效電晶體(NMOS)輸入,p通道金氧半場效電晶體(PMOS)為負載的單級放大器,已經在先前的成果[1]被證實,這種放大器可以提供更好的轉換效率。雖然這種放大器提升了功率效率,但是這種放大器帶來的負面效果是線性度的問題。在第一級解多位元是一個直接的解決辦法,然而這種做法會使得比較器的數目增加,並且對於比較器的偏移電壓容忍度更小。因此在此篇論文中,提出了粗級(coarse stage)輔助微級(fine stage)的概念。這種方式不僅僅在第一級解了四點五的位元而且也降低了比較器的數目,以及對於比較器的偏移電壓有更大的容忍度。
此次提出的類比數位轉換器已經於九十奈米製程中實現,核心電路所需要的晶片面積為0.15平方毫米。而此類比數位轉換器在一伏特的供給下,消耗了8.7毫瓦。實驗的結果顯示在輸入頻率為5.1-MHz下,信噪失真比(SNDR)約為57.23分貝,且在輸入頻率接近奈奎斯特頻率時,信噪失真比(SNDR)約為55.95分貝。另外在輸入頻率在整個奈奎斯特頻率的範圍內,信噪失真比(SNDR)皆高於55分貝。此篇論文的類比數位轉換器在每次轉換時所需要的能量約為42fJ。


Analog-to-digital (A/D) converters which have been a communicator between the analog world and digital domain are indispensable building block in many systems.
In this dissertation, a 10-bit 400-MS/s pipeline ADC is proposed to achieve low power in a 90-nm CMOS technology. On the other hand, amplifiers, important and indispensable block of pipeline ADCs, consume significant power to ensure the performance. A prior art [1] employing a single-stage amplifier consisting of a NMOS differential pair with a PMOS load in pipeline ADCs has been proved that amplifier can provide better conversion-efficiency while achieving better FoM. Although the amplifier increases the power-efficiency, it also introduces the ineluctable linearity issue. A multi-bit front-end stage is a straightforward solution but the solution increases the number of comparators and makes the front-end stage more sensitive to the offset. Hence, this work proposes a coarse-stage-assisted front-end stage that not only resolves 4.5-bit in the first stage but also reduces the number of comparators and becomes less sensitive to the offset.
The proposed ADC has been fabricated in a 90-nm standard CMOS technology which occupies 0.15mm2. The proposed ADC consumes 8.7 mW from a 1-V supply and achieves an SNDR of 57.23 dB at a 5.1-MHz input and 55.95 dB near Nyquist rate. It also achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band. The figure-of-merit (FoM) of the proposed ADC is 42 fJ/Conv.


誌謝 i
摘要 ii
Abstract iii
Contents iv
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Fundamentals of Analog-to-Digital Converters 4
2.1 Introduction 4
2.2 ADC Performance Metrics 4
2.2.1 Differential and Integral Nonlinearity (DNL, INL) 4
2.2.2 Signal-to-Noise Ratio (SNR) 7
2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 8
2.2.4 Effective Number-of-Bits (ENOB) 9
2.2.5 Spurious-Free Dynamic Range (SFDR) 9
2.2.6 Figure of Merit (FoM) 10
2.3 Architectures of Analog-to-Digital Converters 10
2.3.1 Flash Architecture 11
2.3.2 Two-Step and Sub-Ranging Architecture 12
2.3.3 Pipeline Architecture 13
2.3.4 Cyclic (Algorithmic) Architecture 15
2.4 Digital Error Correction 15
2.4.1 Out of Range Error 16
2.4.2 Over Range Error Correction 17
2.4.3 1.5-Bit Pipeline Stage 20
2.5 Summary 25
Chapter 3 A Single-Channel 10-bit 400-MS/s Pipeline ADC 26
3.1 Introduction 26
3.2 Proposed Architecture 28
3.3 Circuit Implementation 30
3.3.1 Input Sampling Network 31
3.3.2 Bootstrap Switch 32
3.3.3 Opamp Design 33
3.3.4 Capacitor-Interpolation subADC 36
3.3.5 subADC2 and subADC3 39
3.3.6 FlashADC 41
3.3.7 Comparator 42
3.3.8 Clock Buffer 44
3.4 Analysis of Proposed Stage 46
3.5 Power Analysis 53
3.6 Simulation Results 56
3.6.1 Post-Layout Simulation 56
3.6.2 Channel Gain Mismatch simulation 56
3.7 Experimental Results 59
3.7.1 Introduction 59
3.7.2 Measurement Setup 59
3.7.3 Print Circuit Board Design 60
3.7.4 Measurement Results 61
3.8 Summary 64
Chapter 4 Conclusions 65
Bibliography 66



[1]B. Sahoo and B. Razavi, “A 10-b 1-GHz 33-mW CMOS ADC,” IEEE J. of Solid-State Circuits, vol. 48, no. 6, pp. 1442-1452, Jun.2013.
[2]B. N. Fang and J. T. Wu, “A 10-bit 300-MS/s pipelined ADC with digital calibration and digital bias generation,” IEEE J. of Solid-State Circuits, vol. 48, no. 3, pp. 670-683, Mar. 2013.
[3]D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997.
[4]F. Maloberti, Data Converters, Springer, Dordrecht, 2007.
[5]M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communi -cations, Kluwer Academic Publisher, Boston, 2000.
[6]B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b Cyclic RSD A/D Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 957-965, Jul. 1992.
[7]S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
[8]L. Brooks and H.-S. Lee, “A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC,” IEEE J. of Solid-State Circuits, vol. 42, pp. 2677-2687, Dec. 2007.
[9]L. Brooks and H.-S. Lee, “A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 166-167.
[10]J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. of Solid-State Circuits, vol. 44, pp. 1057-1066, Apr. 2009.
[11]I. Ahmed, J. Mulder, and D. A. Johns, “A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18um CMOS Using Capacitive Charge-Pumps,” in ISSCC. Dig. Tech. Papers, Feb. 2009, pp. 164-165.
[12]M. Dessouky et al, “Very Low-Voltage Digital-Audio Delta-Sigma Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping,” IEEE J. of Solid-State Circuits, vol. 36, pp. 349–355, Mar. 2001.
[13]J. Park et al, “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D Converter with 400-MHz Input Bandwidth,” IEEE J. of Solid-State Circuits, vol. 39, no. 8, pp. 1335–1337, Aug. 2004.
[14]A. Graupner, “A Methodology for Offset Simulation of Comparators,” The Designer Guide Community, Oct. 2006.
[15]M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35- m CMOS,” IEEE J. of Solid-State Circuits, vol. 36, pp. 1847–1858, Dec. 2001.
[16]J. Kim, B. S. Leibowitz, J. Ren, and C. J. Madden, “Simulation and analysis of random decision errors in clocked comparators,” IEEE Trans. Circuits Syst. I, vol. 56, no. 8, pp. 1844–1857, Aug. 2009.
[17]Y.-S. Shu, M. J. Kyung, W.-M. Lee, B. S. Song, and B. Pain, “A 10~15-bit 60-MS/s Floating-Point ADC with Digital Gain and Offset Calibration,” IEEE J. of Solid-State Circuits, vol. 44, pp. 2356-2365, Sep. 2009.
[18]S.-T. Ryu, B.-S. Song, and K. Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse,” IEEE J. of Solid-State Circuits, vol. 42, pp. 475-485, Mar. 2007.
[19]S.-C. Lee, K.-D. Kim, J.-K. Kwon, J. Kim, and S.-H. Lee, “A 10-bit 400-MS/s 160-mW 0.13-μm CMOS Dual Channel Pipeline ADC without Channel Mismatch Calibration,” IEEE J. of Solid-State Circuits, vol. 41, pp. 1596-1605, Jul. 2006.
[20]H. C. Yang and D. J. Allstot, “Considerations for Fast Settling Operational Amplifiers,” IEEE Trans. Circuits Syst. I, vol. 37, pp. 326-334, Mar. 1990.
[21]N. Sasidhar, Y.-J. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu, and U.-K. Moon, “A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback,” IEEE J. of Solid-State Circuits, vol. 44, pp. 2392-2401, Sep. 2009.
[22]Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS Pipelined ADC With Over 100-dB SFDR,” IEEE J. of Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.
[23]J. Shen and P. R. Kinget, “A 0.5-V 8-bit 10-MS/s Pipelined ADC in 90-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 43, pp. 787-795, Apr. 2008.
[24]K. Honda, M. Furuta, and S. Kawahito, “A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques,” IEEE J. of Solid-State Circuits, vol. 42, pp. 757-765, Apr. 2007.
[25]A. Verma and B. Razavi, “A 10-Bit 500-MS/s 55-mW CMOS ADC,” IEEE J. of Solid- State Circuits, vol. 44, pp. 3039-3050, Nov. 2009.
[26]D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” IEEE J. of Solid- State Circuits, vol. 43, pp. 1904-1911, Dec. 1998.
[27]S. M. Jamal, D. Fu, C.-J. Chang, P. J. Hurst, and S. H. Lewis, “A 10-b 120- Msample/s Time-Interleaved Analog-to-Digital Converter with Digital Back- ground Calibration,” IEEE J. of Solid- State Circuits, vol. 37, pp. 1618-1627, Dec. 2002.
[28]B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA: McGraw-Hill, 2001.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 陳美華、許銘珊 (2010)。以五大人格理論探討學生喜愛之教師人格特質。休閒暨觀光產業研究 , 5(1-2),13-27。
2. 吳鐵雄、李坤崇、劉佑星、歐慧敏(1996)。大專畢業在職人員在工作價值觀量表之信效度、常模與價值觀組型。測驗年刊,43,173-188。
3. 陳木金(1995)。國民小學教師工作價值觀與其美育教學之相關探討。教育與心理研究,18,139-164。
4. 蔡育佑 (2006)。運動教練工作價值觀與組織承諾關係之研究。體育學報,39(2),107-120。
5. 黃國隆(1995)。台灣與大陸企業員工工作價值觀之比較。本土心理學研究,4,92-147。
6. 吳佳玲 (2011),南部技職院校大學生人格特質與網路禮儀素養之研究,遠東通識學報,5(2),47-78。
7. 張順發、羅希哲(2005)。國小教師工作價值觀與組織承諾關係之研究。國民教育研究學報,14,79-111。
8. 黃英忠、余德成、林營松(1995)。組織氣候、工作特性、人格特質、家庭因素、領導行為與組織承諾間關係之研究-以楠梓加工出口區員工為例。人力資源學報,5,15-39。
9. 康正男 (2001)。台灣職業棒球員工作價值觀契合度與組織承諾、工作滿意之關係。體育學報,32,99-109。
10. 唐大鈞(2001)。工作價值觀與工作特性影響我內部稽核人員工作投入與離職傾向的探討(未出版碩士論文)。國立中山大學人力資源管理研究所,高雄市。
11. 李雯娣 (1999)。國小兒童性格特質之研究(未出版碩士論文)。國立屏東師範學院國民教育研究所,屏東市。
 
無相關點閱論文