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研究生:黃湘婷
研究生(外文):Hsiang-Ting Huang
論文名稱:具變壓器耦合W-Band三倍頻器之研製與鎖相迴路在汽車防撞雷達及生命感測雷達之應用
論文名稱(外文):Design and Analysis of W-Band Transformer-coupled Frequency Tripler and Phase-Locked Loops for Automotive Collision Avoidance and Vital Sign Detection Radar Applications
指導教授:黃天偉
指導教授(外文):Tian-Wei Huang
口試委員:蔡政翰張鴻埜
口試委員(外文):Jeng-Han TsaiHong-Yeh Chang
口試日期:2015-06-09
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:139
中文關鍵詞:注入式鎖定倍頻器壓變器耦合鎖相迴路頻率合成器
外文關鍵詞:injection-locked frequency multipliertransformer-coupledphase-locked loopsfrequency synthesizer
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本篇論文為三倍頻器之研製與鎖相迴路在汽車防撞雷達及生命感測器應用。
在第二章中,提出了一個W-Band使用變壓器耦合技術的注入式鎖定三倍頻器,適用於有寬頻應用需求的射頻前端電路,像是毫米波頻段汽車防撞雷達,車聯網也是未來的應用趨勢。由於W-Band增加了鎖定迴路實現的困難性,因此該電路藉由三倍頻器結合變壓器耦合技術將K-Band的訊號被增至W-Band,並有一個Marchand Balun 將單端的輸入訊號轉成雙端差動訊號,激發電晶體的非線性特性,產生倍頻的效果,再注入變壓器耦合的共振腔鎖定,進而達到寬頻、降低功耗、縮小晶片面積的特色。
在第三章中,提出一組K-Band的本地震盪源,由低頻的整數型鎖相迴路和三倍頻器組成,具有寬頻、低相位雜訊、低功耗的特性,可應用於24 GHz 的汽車防撞雷達系統的射頻前端電路。該壓控震盪器採用NMOS架構,三倍頻器使用單端平衡式混波器方法,藉由混頻壓控震盪器產生出來一階和二階諧波項,進而得到三倍頻率,加上在壓控震盪器之交錯耦合對共模點的二階諧波利用並聯阻抗提升的技巧,有效降低三倍頻器的相位雜訊。
在第四章中,提出X-Band的整數型及小數型鎖相迴路,應用於生命訊號偵測雷達系統或可攜式微型寬頻生理訊號偵測雷達晶片組。該電路使用運算放大器型的充電汞,可降低充放電之電流不匹配問題,寬頻率範圍的多頻帶之互補式壓控震盪器,具有寬頻、低相位雜訊、低功耗之特性。
論文的第一章和第五章分別是論文的動機介紹和本碩士論文完成的研究結論。


In this thesis, we present the design, analysis, and implement for three CMOS millimeter-wave integrated circuits. Including W-Band transformer-coupled frequency tripler, K-band LO generator for automotive collision avoidance and X-band phase-locked loops vital sign detection radar applications.
In chapter 2, the W-band injection-locked frequency tripler using bandwidth-enhanced transformer-coupled technique is proposed. Smart cars are the future application trend, which require the internet of vehicles (IOV) and autopilot functions. Through a Marchand balun, the K-band input signal can be converted into differential signals. This frequency tripler is adequate to generate W-band signal with the advantages of wide bandwidth, good phase noise, low dc power and small chip size.
In chapter 3, the direct combination of a 8-10 GHz PLL with a 24 GHz frequency tripler for K-band Local Oscillator (LO) generation is proposed. The power consumption can be reduced without inserting a buffer stage between the VCO and the mixer-type tripler. With the shunt-peaking technique at second harmonic, it can improve the phase noise in VCO and results in better phase noise in frequency tripler output.
In chapter 4, the proposed X-band fraction-N Phase-Locked Loop with lower phase noise and low dc consumption is proposed and is for vital sign detection radar application. To decrease the phase noise and increase the tuning range, we achieve small K_VCO using band-switching complementary LC VCO. The operation-amplifier type charge pump successfully solves the current mismatch problem. A MASH 111 with 6-bit 3-order delta–sigma modulator is used in this fractional-N frequency synthesizer.


口試委員會審定書 #
誌謝 i
中文摘要 ii
Abstract iii
CONTENTS iv
LIST OF FIGURES viii
LIST OF TABLES xvii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 A 3.7 mW 75-87-GHz Injection-locked Frequency Tripler Using Bandwidth-enhanced Transformer-coupled Topology for Automatic Radar Applications 3
2.1 Introductions 3
2.2 Analysis of Injection-locked Frequency Multiplier using Transformer-coupled Technique 6
2.2.1 Analysis of Injection-locked 6
2.2.2 Analysis of the locking range 11
2.2.3 Analysis of the model of ILFT 15
2.2.4 Transformer-coupled Design Technique 18
2.2.5 Analysis of the negative resistance 21
2.2.6 Analysis of the degradation of phase noise of the injection-locked frequency multiplier 22
2.3 Circuit Design of a 3.7 mW 75-87-GHz Injection-locked Frequency Tripler Using Bandwidth -enhanced Transformer-coupled Topology 25
2.4 Simulation and Experimental Results 30
2.4.1 Simulation Results 32
2.4.2 Experimental Results 36
2.5 Summary 42
Chapter 3 A PLL and Frequency Tripler for K-band Local Oscillator Generation and 24 GHz Automatic Radar Applications) 44
3.1 Introduction 44
3.2 Basic of Phase-Locked Loops and Multipliers 45
3.2.1 Analysis of Loop Bandwidth and Passive Loop Filter 45
3.2.2 Analysis of VCO Phase Noise: White Noise and Flicker Noise 50
3.2.3 Analysis of Phase Noise of Frequency Multipliers and Dividers 53
3.3 Proposed Architecture of 8 GHz PLL and 24 GHz Frequency Tripler and for K-band Local Oscillator Generation 54
3.4 Circuit Design of the PLL and Frequency Tripler for K-band Phase-Locked Loops Application 55
3.4.1 Voltage-Controlled Oscillator (VCO) 55
3.4.2 Frequency Tripler 58
3.4.3 Current Mode Logic (CML) Divider 61
3.4.4 True Single Phase Clock (TSPC) Divider 62
3.4.5 Multi-Modulus Frequency Divider (MMD) 63
3.4.6 Phase Frequency Detector (PFD) 64
3.4.7 Charge Pump (CP) 65
3.5 Simulation and Experimental Results 66
3.5.1 Simulation Results 66
3.5.2 Experimental Results 73
3.6 Discussion 85
3.7 Summary 87
Chapter 4 A X-Band Phase-Locked Loop in 0.18 μm CMOS Technology for Vital Sign Detection Radar Application 88
4.1 Introduction 88
4.2 Phase-Locked Loops Basic 90
4.2.1 Phase Lock Loop Phase Noise Analysis 90
4.2.2 Basic of Integer-PLL and Fractional-PLL 93
4.2.3 Analysis of Non-ideal Effect in Charge Pump 95
4.2.4 Analysis of Band-Switching for Multiband VCO 97
4.3 Design Procedure 99
4.3.1 Design Procedure of Proposed Voltage-Controlled Oscillator 99
4.3.2 Design Procedure of the Proposed Phase-Locked Loops 100
4.4 Proposed Architecture of X-Band Phase-Locked Loop 101
4.5 Circuit Design of a X-Band Phase-Locked Loop in 0.18 um CMOS Technology for Vital Sign Detection Radar Application 102
4.5.1 Voltage-Controlled Oscillator (VCO) 102
4.5.2 Current Mode Logic (CML) Divider and D2S 104
4.5.3 True Single Phase Clock (TSPC) Divider 105
4.5.4 Multi-Modulus Frequency Divider (MMD) 106
4.5.5 Phase Frequency Detector (PFD) 107
4.5.6 Charge Pump (CP) 109
4.5.7 Mash 111 Delta Sigma Modulator 111
4.6 Simulation and Experimental Results 114
4.6.1 Simulation Results 114
4.6.2 Experimental Results 120
4.7 Summary 130
Chapter 5 Conclusions 131
REFERENCE 132
PUBLICATIONS 139


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