跳到主要內容

臺灣博碩士論文加值系統

(44.192.22.242) 您好!臺灣時間:2021/08/03 20:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:趙鈞彥
研究生(外文):Chun-Yen Chao
論文名稱:互補式金氧半導體功率放大器之功率結合技術以及改善回推效率與線性度研究
論文名稱(外文):Research on Power Combining Technique and Improving Linearity and Back-off Efficiency for CMOS Power Amplifier
指導教授:林坤佑林坤佑引用關係
口試委員:張鴻埜蔡政翰蔡作敏傅家相
口試日期:2015-07-23
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:161
中文關鍵詞:毫米波互補式金氧半導體功率放大器功率結合回推效率線性化
外文關鍵詞:mmWaveCMOSpower amplifierpower combiningback-offefficiencylinearization
相關次數:
  • 被引用被引用:0
  • 點閱點閱:153
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
這篇論文共提出三個功率放大器,分別利用Doherty放大器、低頻二階項前饋、以及多路功率結合來提升放大器的回推效率、線性度以及輸出功率。
第一顆晶片是使用180奈米互補式金氧半導體製作一個操作在K 頻段且具有改善回推效率功能的改良式Doherty功率放大器。此功率放大器串接兩級放大器來達到更高的增益。在輸出級分成主路徑和附屬路徑,主路徑是AB類的共源極放大器,目的是為了在小訊號時有足夠的增益。附屬路徑是偏壓接近B類放大器的AB類疊接式放大器,目的是為了在大訊號時有不錯的增益,但在小訊號時消耗較少功耗,以提升放大器的回推效率。在功率分配的地方此電路使用了不均勻功率分配器以及相位補償傳輸線來提升回推效率和1-dB 壓縮點的輸出功率。根據在22 GHz量測的結果,此電路具有13.7 dB的小訊號增益,在飽和輸出功率時有17.2 dBm的輸出功率和24.8%的功率附加效率。而在1-dB 壓縮點有16.3 dBm的輸出功率和21.5%的功率附加效率。而在6-dB回推點有11.5%的功率附加效率。
第二顆晶片是使用90奈米互補式金氧半導體製作一個操作在60 GHz並利用低頻二階項前饋技術改善線性度的功率放大器。此功率放大器串接兩級放大器來達到更高的增益。電路包含主要放大器及線性器。主要放大器是由疊接組態組成,用來提供足夠的增益,而線性器產生與主路徑相同大小但相位相反的三階項電流來消除三階項電流。另外藉疊接組態電流鏡和直流位準移位器設計二階項電流以產生足夠的三階項電流。根據模擬結果,此電路具有15 dB的小訊號增益,在飽和輸出功率時有15.2 dBm的輸出功率和13%的功率附加效率。而在1-dB 壓縮點有13.9 dBm的輸出功率和11.5%的功率附加效率。三階項訊號在甜蜜點改善了大約20 dBc。根據量測結果,附屬路徑的直流電流和模擬有誤差,後文會附上偵錯結果。
第三顆晶片是使用90奈米互補式金氧半導體製作一個操作在E頻段並利用多路功率結合技術提升輸出功率的功率放大器。此功率放大器串接三級放大器來達到更高的增益。其中第二級使用16路功率結合,而第三級使用32路功率結合以輸出更多功率。在此兩級使用多路功率技術結合技術能使偏壓電路更簡單並提升操作頻寬。根據模擬結果,此電路在整個E頻段具有10~11.8 dB的小訊號增益,在飽和輸出功率時有15.3~16.1 dBm的輸出功率和6.8~8%的功率附加效率。而在1-dB 壓縮點有12.8~13.7 dBm的輸出功率。根據量測結果,小訊號增益在10 dB以下,和模擬有誤差。此外輸入端反射係數和模擬有差異,後文會附上偵錯結果。


In this thesis, a K-band modified Doherty power amplifier, a V-band PA using low-frequency IM2 feed-forward method, and a E-band PA using multi-way power combining technique are proposed to improve the back-off efficiency, linearity, and output power of CMOS power amplifiers respectively.
First, a K-band modified Doherty power amplifier fabricated in 0.18-μm CMOS technology is proposed to improve the back-off efficiency. The proposed power amplifier consists of two stages for higher gain. The output stage is composed of main and auxiliary paths. The main path consists of common source topology and is biased at class-AB to provide enough gain at small signal. The auxiliary path consists of cascode topology and is biased at class-AB near class B to provide high gain at large signal and to save dc power consumption for small-signal operation. The uneven power splitter and phase-compensation line are used in power splitting to improve the back-off efficiency and OP1dB. According to the measurement results at 22 GHz, the proposed PA provides 13.7-dB small signal gain, 16.3-dBm OP1dB and 17.2-dBm Psat. The peak power-added-efficiency (PAE), PAE at OP1dB, and PAE at 6-dB back-off are 24.8%, 21.5%, and 11.5% respectively.
Second, a low-frequency IM2 feed-forward method is used to improve the linearity of the 60 GHz CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of two stage for higher gain. The power stage consists of main amplifier and linearizer. The main amplifier consists of cascode topology to provide enough gain. The linearizer consists of two transistors to provide the same magnitude and inverse phase of IM3 current compared to the main amplifier to cancel the IM3 current at the output. The cascode current mirror and DC-level shifter are used to feed the IM2 current in the linearizer. According to the simulation results, the PA provides 15-dB small signal gain, 13.9-dBm OP1dB and 15.2-dBm Psat. The peak PAE and PAE at OP1dB is 13% and 11.5%, respectively. The IM3 signal is reduced about 20 dBc at sweet-spot. According to the measurement results, the dc current of the auxiliary path is different from that of the simulation result. The debug result is provided.
Third, a multi-way power combining technique is used to increase the output power of the E-band CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of three stage for higher gain. The second and third stages are 16-way and 32-way combining respectively for higher output power. The power combining technique applied in the two stages can simplify the layout of bias circuit and achieve wideband matching. According to the simulation results from 71 to 86 GHz, the PA provides 10~11.8-dB small signal gain, 12.8~13.7-dBm OP1dB and 15.3~16.1-dBm Psat. The peak PAE is 6.8~8%. According to the measurement results, the gain is below 10 dB, and it is different from the simulation. Besides, the input return loss is different from the simulation result. The debug result is provided.


口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES xi
LIST OF TABLES xxi
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Literature Survey 1
1.2.1 K-band power amplifiers 1
1.2.2 V-band power amplifier 2
1.2.3 E-band power amplifier 3
1.3 Contributions 4
1.4 Thesis organization 6
Chapter 2 Overview of Power Amplifier 7
2.1 Introduction 7
2.2 Important parameters 7
2.2.1 Power 7
2.2.2 Efficiency 8
2.2.3 Linearity 9
2.3 Linearization Technique 14
2.3.1 Feed-forward [12] 14
2.3.2 Pre-distortion [8] 15
2.4 Increasing Back-off Efficiency Technique 16
2.4.1 Doherty Power Amplifier [2] 16
2.4.2 Adaptive bias [6] 18
Chapter 3 24 GHz Modified Doherty Power Amplifier 19
3.1 Motivation 19
3.2 Main Path 22
3.2.1 Gate bias 22
3.2.2 Topology 22
3.2.3 Size 24
3.3 Auxiliary Amplifier 27
3.3.1 Class-C CS amplifier 27
3.3.2 Class-C cascode amplifier 28
3.3.3 Cascode amplifier biased at deep class AB 29
3.3.4 Two combined cascode amplifier biased at deep class AB 30
3.4 Matching Network of Power Stage 31
3.4.1 Output matching 31
3.4.2 Bypass capacitor and test line 35
3.4.3 Uneven power splitter 38
3.4.4 Phase compensation line 43
3.5 Driver Stage 44
3.5.1 Driver amplifier 44
3.5.2 Inter-stage matching 45
3.5.3 Input matching 47
3.5.4 Gate voltage of M4 48
3.6 Simulation 50
3.6.1 Small signal 52
3.6.2 Stability 53
3.6.3 Large signal 55
3.6.4 IMD3 55
3.7 Measurement 56
3.7.1 Small signal 57
3.7.2 Large signal 59
3.8 Revised simulation 63
3.9 Summary 67
Chapter 4 60 GHz Linearized Power Amplifier with Successive Second Order Inter-modulation (IM2) Feed-forward Technique 70
4.1 Introduction 70
4.2 Main path 71
4.2.1 Gate bias 71
4.2.2 Topology 71
4.2.3 Size of amplifiers in output stage 72
4.2.4 Output matching 75
4.2.5 Driver stage and inter-stage matching 77
4.2.6 Input matching 79
4.3 Theory of auxiliary path 80
4.3.1 Output IM3 current of the auxiliary path 80
4.3.2 Voltage bias of the transistors 82
4.3.3 Size of the transistors 84
4.4 Implement of the auxiliary path 91
4.4.1 Current mirror 92
4.4.2 DC-level shifter 96
4.4.3 The resistor R1 101
4.5 Simulation result 103
4.5.1 Small-signal Simulation Results 105
4.5.2 Large-signal Simulation Results 106
4.5.3 Stability 108
4.5.4 IM3 and IMD3 110
4.6 Measurement (version 1) 112
4.6.1 Small signal 114
4.6.2 Debug 115
4.7 Measurement (version 2) 120
4.7.1 Small signal 122
4.7.2 Problem 123
4.8 Debug and summary 124
4.8.1 Debug 124
4.8.2 Summary 125
Chapter 5 71-86 GHz Wideband Power Amplifier 126
5.1 Introduction 126
5.2 Active devices 126
5.2.1 Bias 126
5.2.2 Topology 127
5.2.3 Size 128
5.3 Design of the PA 130
5.3.1 Bus-bar technique for dc biasing [28] 130
5.3.2 Output stage 132
5.3.3 Power budget 135
5.3.4 Second stage 135
5.3.5 First stage 136
5.3.6 Odd mode resistance [28] 139
5.4 Simulation result 140
5.4.1 Small-signal Simulation Results 142
5.4.2 Large-signal Simulation Results 143
5.4.3 Stability 145
5.5 Measurement and debug 148
5.5.1 Small signal 149
5.5.2 Debug 150
5.5.3 Summary 154
Chapter 6 Conclusion 155
REFERENCE 157



[1]K. M. Strohm, H. L. Bloecher, R. Schneider, and J. Wenger, “Development of future short range radar technology,” in Radar Conference, 2005, pp. 165–168.
[2]Daehyun Kang, Jinsung Choi, Dongsu Kim, and Bumman Kim,” Design of Doherty power amplifiers for handset applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 8, Aug 2010, pp. 2134–2142.
[3]Y.-N. Jen, J.-H. Tsai, C.-T. Peng, and T.-W. Huang, “A 20 to 24 GHz +16.8 dBm fully integrated power amplifier using 0.18-μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, Jan. 2009, pp.42-44.
[4]P.-C. Huang, J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 22-dBm 24-GHz power amplifier using 0.18-μm CMOS technology,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp.248–251.
[5]C.-C. Hung, J.-L. Kuo, K.-Y. Lin, and H. Wang, “A 22.5-dB gain, 20.1-dBm output power K-band power amplifier in 0.18-μm CMOS process,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., May 2010, pp. 557–560.
[6]N.-C. Kuo, J.-C. Kao, C.-C. Kuo, and H.Wang, “K-band CMOS power amplifier with adaptive bias for enhancement in back-off efficiency,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4.
[7]Y.-C. Hsu, Y.-S. Chen, T.-C. Tsai, and K.-Y. Lin, “A K-band CMOS cascade power amplifier using optimal bias selection methodology,” in Proc. Asia-Pacific Microw. Conf., Dec. 2011, pp. 793–796.
[8]Kun-Yao Kao, Yu-Chung Hsu, Kuan-Wei Chen, and Kun-You Lin, “Phase-delay cold-FET pre-distortion linearizer for millimeter-wave CMOS power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 12, Dec 2013, pp. 4505–4519.
[9]Jeng-Han Tsai and Tian-Wei Huang, “A 38–46 GHz MMIC Doherty power amplifier using post-distortion linearization,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, May. 2007, pp.388-390.
[10]Ercan Kaymaksut, Dixian Zhao and Patrick Reynaert, “E-band transformer-based Doherty power amplifier in 40 nm CMOS,” Radio Frequency Integrated Circuits Symposium, 2014, pp. 167 - 170.
[11]B. Wicks et al., “A 60-GHz fully-integrated Doherty power amplifier based on 0.13-um CMOS process,” Radio Frequency Integrated Circuits Symposium, 2008, pp. 69 - 72.
[12]D. G. Kim, N. P. Hong, and Y. W. Choi, “A Novel Linearization Method of CMOS Drive Amplifier Using IMD Canceller,” in IEEE Microw. Wireless Compon. Lett., vol. 10, pp. 671-673, Oct. 2009.
[13]M. Bohsali and A. M. Niknejad, “Current combining 60 GHz CMOS power amplifiers,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2009, pp. 31–34.
[14]T. Quemerais, L. Moquillon, J.-M. Fournier, P. Benech, and V. Huard, “Design-in-reliable millimeter-wave power amplifiers in a 65-nm CMOS process,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 4, pp. 1079–1085, Apr. 2012.
[15]J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 50 to 70 GHZ power amplifier using 90 nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 45–47, Jan. 2009.
[16]M. Abbasi, T. Kjellberg, A. d. Graauw, E. v. d. Heijden, R. Roovers, and H. Zirath, “A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHZ system-on-chip,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., May 2010, pp. 533–536.
[17]Y.-N. Jen, J.-H. Tsai, T.-W. Huang, and H. Wang, “Design and analysis of a 55–71 GHz compact and broadband distributed active transformer power amplifier in 90 nm CMOS process,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1637–1646, Jul. 2009.
[18]Y. He, L. Li, and P. Reynaert, “60GHz power amplifier with distributed active transformer and local feedback,” in Proc. ESSCIRC, Sep. 2010, pp. 314–417.
[19]S. Aloui, B. Leite, N. Demirel, R. Plana, D. Belot, and E. Kerherve, “High-gain and linear 60-GHz power amplifier with a thin digital 65-nm CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 6, pp. 2425–2437, Jun. 2013.
[20]J. Essing, R. Mahmoudi, Y. Pei, and A. v. Roermund, “A fully integrated 60 GHz distributed transformer power amplifier in bulky CMOS 45 nm,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2011, pp. 1–4.
[21]E. Cohen, S. Ravid, and D. Ritter, “60 GHz 45 nm PA for linear OFDM signal with predistortion correction achieving 6.1% PAE and EVM,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2009, pp. 35–38.
[22]J.-H. Tsai, C.-H. Wu, H.-Y. Yang, and T.-W. Huang, “A 60 GHZ CMOS power amplifier with built-in pre-distortion linearizer,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 12, pp. 676–678, Dec. 2011.
[23]J. Y.-C. Liu,Q. J. Gu, A. Tang, N.-Y. Wang, and M.-C. F. Chang, “A 60 GHZ tunable output profile power amplifier in 65 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 8, pp. 377–379, Jul. 2011.
[24]J. Y.-C. Liu, R. Berenguer, and M.-C. F. Chang, “Millimeter-wave self-healing power amplifier with adaptive amplitude and phase linearization in 65-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1342–1352, May 2012.
[25]K.-Y.Wang, T.-Y. Chang, and C.-K.Wang, “A 1 V 19.3 dBm 79 GHz power amplifier in 65 nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2012, pp. 260–262.
[26]T. Suzuki, Y. Kawano, M. Sato, T. Hirose, and K. Joshin, “60 and 77 GHz power amplifiers in standard 90 nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2008, pp. 562–563.
[27]N. Demirel, E. Kerhervé, R. Plana, and D. Pache, “79 GHz BiCMOS single-ended and differential power amplifiers,” in Proc. IEEE Eur. Microw. Conf., Sep. 2010, pp. 1690–1693.
[28]Y. H. Hsiao, Z. M. Tsai, H. C. Liao, J. C. Kao, and H. Wang, “Millimeter-wave CMOS power amplifiers with high output power and wideband performances,” IEEE Trans. Microw. Theory Tech, vol. 61, no. 12, pp. 4520–4533, Dec 2013.
[29]D. Chan and M. Feng, “A compact W-band CMOS power amplifier with gain boosting and short-circuited stub matching for high power and high efficiency operation,” Proc. IEEE Microw. Wireless Compon. Lett., vol. 21, pp. 98–100, Feb. 2011.
[30]J. Oh, B. Ku, and S. Hong, “A 77-GHz CMOS power amplifier with a parallel power combiner based on transmission-line transformer,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 7, pp. 2662–2669, Jul. 2013.
[31]A. Komijani and A. Hajimiri, “A wideband 77-GHz, 17.5-dBm fully integrated power amplifier in silicon,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1749–1756, Aug. 2006.
[32]R. B. Yishay, R. Carmon, O. Katz, and D. Elad, “A high gain wideband 77 GHz SiGe power amplifier,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2010, pp. 529–532.
[33]V. Giammello, E. Ragonese, and G. Palmisano, “A 15-dBm SiGe BiCMOS PA for 77-GHz automotive radar,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 11, pp. 2910–2918, Nov. 2011.
[34]V. Giammello, E. Ragonese, and G. Palmisano, “A transformer-coupling current-reuse SiGe HBT power amplifier for 77-GHz Automotive Radar,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 6, pp. 1676–1683, Jun. 2012.
[35]A. Y.-L. Chen, Y. Baeyens, Y.-K. Chen, and J.-S. Lin, “An 83-GHz high-gain SiGe BiCMOS power amplifier using transmission-line current combining technique,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1557–1569, Apr. 2013.
[36]Yi-Hsin Chen, Kun-Yao Kao, Chun-Yen Chao, and Kun-You Lin, “A 24 GHz CMOS Power Amplifier with Successive IM2 Feed-Forward IMD3 Cancellation,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., May. 2015.
[37]陳譯心 “利用低頻二階項前饋方法之24 GHz互補式金氧半導體線性化功率放大器之研製Research on 24 GHz CMOS Linearized Power Amplifier Using Low Frequency IM2 Feed-forward Method” 國立台灣大學電信工程研究所碩士論文, 民國101 年六月, 2012.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 12.李瑞典,戰時刑事訴訟程序芻議,軍法專刊,臺北市,第49卷第7期,2003年7月。
2. 13.李瑞典,中共軍事審判制度,軍法專刊,臺北市,第50卷第12期,2004年12月。
3. 14.李瑞典,軍法觀護工作回顧與前瞻,軍法專刊,臺北市,第52卷第3期,2006年6月。
4. 15.李瑞典、吳純顯,兩岸軍事刑法之研究,軍法專刊,臺北市,第53卷第6期,2007年12月。
5. 22.郭欽銘,海峽兩岸刑法之比較研析(上),軍法專刊,第48卷第1期,臺北市,2002年1月。
6. 23.郭欽銘,海峽兩岸刑法之比較研析(下),軍法專刊,第48卷第2期,臺北市,2002年2月。
7. 34.趙晞華,陸海空軍刑法立法體例及規範目的之研究,刑事法雜誌,第48卷第6期,臺北市,2002年3月。
8. 36.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(一),軍法專刊,第47卷第10期,臺北市,2001年10月。
9. 37.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(二),軍法專刊,第47卷第11期,臺北市,2001年11月。
10. 38.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(三),軍法專刊,第47卷第12期,臺北市,2001年12月。
11. 39.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(四),軍法專刊,第48卷第2期,臺北市,2002年2月。
12. 40.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(五),軍法專刊,第48卷第4期,臺北市,2002年4月。
13. 41.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(六),軍法專刊,第48卷第7期,臺北市,2002年7月。
14. 42.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(七),軍法專刊,第48卷第8期,臺北市,2002年8月。
15. 43.謝添富、趙晞華,陸海空軍刑法修正經過及修正內容析述(八),軍法專刊,第48卷第9期,臺北市,2002年9月。
 
無相關點閱論文