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研究生:梁中明
研究生(外文):Chung-Ming Liang
論文名稱:以嵌入式系統與IEEE 1588實作微型相量量測器
論文名稱(外文):Implementation of Micro Phasor Measurement Unit (μPMU) Using Embedded System and IEEE 1588
指導教授:劉志文劉志文引用關係
口試委員:盧展南黃世杰蔡孟伸
口試日期:2015-07-28
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:57
中文關鍵詞:廣域量測系統嵌入式系統同步相量量測IEEE 1588
外文關鍵詞:Wide-area monitoring systemEmbedded systemSynchrophasor measurementIEEE 1588
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Synchronous phasor measurement units (PMUs) are data acquisition devices utilized in wide-area monitoring systems (WAMS). They are installed at selected buses, sampling three-phase voltage and three-phase current to calculate the phasor. The capability of receiving Global Positioning System (GPS) signals such as time tag and 1- pulse-per-second signal synchronizes phasor data collected all over the power grid. Synchrophasors in real-time applications are used to monitor the status of the power system so as to, when fault occurs, enable operators to take proper measures as soon as possible. In non-real-time applications, researchers analyze these data to find the cause of the event in the hope of preventing similar events from reoccurring. Nevertheless, if failing to receive correct GPS signals in any case, PMUs are not able to be synchronized, and the acquired data are rendered valueless. Moreover, equip every PMU with GPS signal receiver will raise the cost. Hence, this research uses IEEE 1588 to achieve synchronization with cheaper computer network system, and has higher reliability than the ones depending on GPS systems.

Contents
致 謝 ii
摘 要 iii
Abstract iv
Contents v
List of Figures vii
Chapter 1 Introduction 1
1-1 General Background Information 1
1-2 Research Purpose and Contribution 2
1-3 Literature Review 2
1-4 Abstract of Each Chapter 3
Chapter 2 The Development Platform of the μPMU 5
2-1 Overview 5
2-2 Topology 5
2-3 CompactRIO 9024 6
2-3-1 Features 7
2-3-2 Hardware Specification 8
2-3-3 Integrated Development Environment 9
2-4 PCI-1588 11
2-4-1 Features 12
2-5 IEEE 1588 (Precision Time Protocol, PTP) [16] 12
Chapter 3 The Implementation of the μPMU 17
3-1 Overview 17
3-2 Phasor Estimation Algorithm 17
3-2-1 Recursive Calculation of DFT 18
3-2-2 SDFT 20
3-2-3 Implementation of SDFT 24
3-3 Software Structure of the Program 24
3-3-1 FPGA Module 26
3-3-2 Real-Time Module 27
3-3-3 Data Transfer Between FPGA and Real-Time Module 27
3-3-4 Synchronization Between FPGA and Real-Time Module 30
3-4 Acquiring Time Information via PCI-1588 31
3-4-1 Retrieving Time Signal 32
3-4-2 Processing Time Signal 37
3-5 Voltage Signal Acquisition 41
3-5-1 Voltage Signal Acquisition in FPGA Module 42
3-5-2 Process Voltage Signals in RT Module 46
3-6 Combine Voltage Signal Acquisition with Time Tagging 51
Chapter 4 Conclusion and Future Research 54
4-1 Conclusion 54
4-2 Future research 54
Bibliography 55


List of Figures
Figure 2-1: The topology of the μPMU 6
Figure 2-2: Data flow in side CompactRIO 7
Figure 2-3: The Front Panel in LabVIEW 10
Figure 2-4: The Block Diagram in LabVIEW 11
Figure 2-5: IEEE 1588 synchronization mechanism and delay calculation 14
Figure 3-1: The initial sliding window 19
Figure 3-2: The sliding window after one sampling period 19
Figure 3-3: Consecutive runs of DFT 20
Figure 3-4: The Project Window of LabVIEW 25
Figure 3-5: Create a FIFO 28
Figure 3-6: The General category in the Properties window 29
Figure 3-7: The Data Type category in the Properties window 29
Figure 3-8: IRQ in FPGA module 31
Figure 3-9: IRQ-related functions in RT module 31
Figure 3-10: NI Measurement & Automation Explorer (NI MAX) 33
Figure 3-11: Test Panels 33
Figure 3-12: Schema of time signal receiving process in Host Computer 34
Figure 3-13: The niSync Set Time function icon 35
Figure 3-14: The loop to verify whether the time information is valid 36
Figure 3-15: The program configuring internet settings 36
Figure 3-16: The program sending time info to RT module 37
Figure 3-17: Schema of time signal processing in RT module 38
Figure 3-18: The program configuring internet settings 39
Figure 3-19: Process time information 40
Figure 3-20: Call the program in FPGA module 40
Figure 3-21: The loop sends time information to FPGA module 41
Figure 3-22: End the link to FPGA module 41
Figure 3-23: Schema of receiving signals in the FPGA module 42
Figure 3-24: Set sampling frequency 44
Figure 3-25: Start the voltage acquisition function 44
Figure 3-26: Sample the voltage and send results to Data FIFO 45
Figure 3-27: Pause the program and turn to RT module 45
Figure 3-28: Stop the voltage acquisition function 45
Figure 3-29: The Front Panel of the program in FPGA module 46
Figure 3-30: Schema of the program in RT module 47
Figure 3-31: Link to FPGA program and reset all the parameters 49
Figure 3-32: Set sampling rate and the number of data retrieved from Data FIFO 49
Figure 3-33: Run the program in FPGA module 49
Figure 3-34: Use IRQ to read sampled voltage data 50
Figure 3-35: Check if there are any error and whether FIFO is full 50
Figure 3-36: End the link to FPGA module 51
Figure 3-37: The Front Panel of the RT module with a waveform of the voltage signal 51
Figure 3-38: Schema of the voltage and time acquisition program 52
Figure 3-39: Content of the loop of the voltage and time acquisition program 53




Bibliography
[1] Z. Zhong, C. Xu, B. J. Billian, L. Zhang, S.-J.S. Tsai, R. W. Conners, V. A. Centeno, A. G. Phadke, and Y. Liu, “Power system frequency monitoring network (FNET) implementation,” IEEE Trans. Power Syst., vol. 20, no. 4, pp. 1914–1921, Nov. 2005.
[2] H. Karimi et al., “Estimation of frequency and its rate of change for applications in power systems,” IEEE Trans. Power Del., vol. 19, no. 2, pp. 472–480, Apr. 2004.
[3] Y. Zhang, P. Markham, T. Xia, L. Chen, Y. Ye, Z. Wu, Z. Yuan, L. Wang, J. Bank, J. Burgett, R. W. Conners, and Y. Liu,“Wide-area frequency monitoring network (FNET) architecture and applications,” IEEE Transaction on Smart Grid, Vol. 1, No. 2, pp. 159-167, Sept. 2010.
[4] Q. Bin, L. Chen, V. Centeno, X. Z. Dong, and Y. Liu, “Internet based frequency monitoring network (FNET),” in Proc. 2001 IEEE Power Eng. Soc. Winter Meet., pp. 1166–1171.
[5] Y. Liu, “A US-wide power systems frequency monitoring network,” in Proc. 2006 IEEE Power Eng. Soc. Gen. Meet., p. 8.


[6] R. M. Gardener and Y. Liu, “FNET: A quickly deployable and economic system to monitor the electric grid,” in Proc. 2007 IEEE Conf. Technol. Homeland Security, pp. 209–214.
[7] 庄玉飞, 黄琦, and 井实. "基于 GPS 和 IEEE-1588 协议的时钟同步装置的研制." 电力系统保护与控制 39.13 (2011): 111-115.
[8] Pallares-Lopez, Victor, et al. "Synchrophasor for smart grid with IEEE 1588-2008 synchronism." Prz. Elektrotechniczny 88.1A (2012): 31-36.
[9] Fodero, K., C. Huntley, and D. Whitehead. "Secure, Wide-Area Time Synchronization." proceedings of the 12th Annual Western Power Delivery Automation Conference, Spokane, WA. 2010.
[10] Carta, Andrea, et al. "GPS and IEEE 1588 synchronization for the measurement of synchrophasors in electric power systems." Computer Standards & Interfaces 33.2 (2011): 176-181.
[11] Lijun, Qin, et al. "Feasibility study of PMU based on IEEE 1588." Electric Utility Deregulation and Restructuring and Power Technologies (DRPT), 2011 4th International Conference on. IEEE, 2011.
[12] Lixia, Marco. "IEEE 1588 synchronization in distributed measurement systems for electric power networks." (2012).
[13] NI CompactRIO, http://www.ni.com/compactrio/zht/
[14] LabVIEW, http://www.ni.com/labview/zht/
[15] NI PCI-1588 Interface, http://sine.ni.com/nips/cds/view/p/lang/en/nid/202345
[16] IEEE 1588 (Precision Time Protocol, PTP), https://en.wikipedia.org/wiki/Precision_Time_Protocol
[17] J.Z Yang and C.W Liu, “A Precise Calculation of Power System Frequency and Phasor,” IEEE Transaction on Power Deliver, Vol. 15, No. 2, pp.494-499, April 2000.
[18] J-Z Yang and C-W Liu, “A New Family of Measurement Technique for Tracking Voltage Phasor, Local System Frequency, Harmonics and DC Offset,” IEEE Power Engineering Society Summer Meeting, Vol. 3, pp. 1327-1332, 2000.
[19] J-Z Yang, C-S Yu, and C-W Liu, “A New Method for Power Signal Harmonic Analysis,” IEEE Transactions on Power Delivery, Vol. 20, Issue 2, 2005, pp.1235 – 1239.
[20] J-Z Yang, C-W Liu, and W-G Wu, “A Hybrid Method for the Estimation of Power System Low-Frequency Oscillation Parameters,” IEEE transactions on Power Systems, Vol. 22, Issue 4, pp. 2115-2123, 2007.
[21] J-Z Yang, “A Two-Stage Combined Method for Harmonic/Interharmonic Analysis,” IEEE Power Engineering Society General Meeting, Calgary, 2009.07.
[22] Introduction to FPGA Technology, http://www.ni.com/white-paper/6984/zht/


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