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研究生:黃永松
研究生(外文):Yung-Sung Huang
論文名稱:適用非對稱多核心處理器之多媒體資料處理之研究
論文名稱(外文):The study of multimedia data processing for asymmetric multi-core processor platform
指導教授:邱炳樟邱炳樟引用關係
口試委員:邱炳樟
口試日期:2015-01-22
學位類別:博士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:93
中文關鍵詞:多媒體資料處理
外文關鍵詞:Multimedia data processing
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當今多媒體與行動裝置的組合已變成主流消費性產品,在這類裝置執行視訊、串流等多媒體訊號處理越來越頻繁,如何讓多媒體訊號處理越順暢,已變成熱門的議題。許多硬體業者會朝增多CPU核心數加速效能,但也有使用GPU (Graphic Processing Unit)或是專門處理數學運算的DSP (Digital Signal Processor)來達到加速影像處理;軟體方面就以達成時間上的滿足為目標,朝管理儲存資料的記憶體、管控程式的程序、與演算程序簡化。綜合上述軟、硬體的獨立的處理方式不可能達到最佳化的效能提升。因此,本論文的研究重點是運用行動裝置的硬體平台的特性,搭配軟體管理去對多媒體處理器的架構做適度的效能調配。
常見硬體效能提升有兩個做法,一是增加CPU的核心數,但是這類處理器是以序列處理,讓執行於作業系統層的播放多媒體的程式增加開發困難,因此不是我們要選擇的硬體平台;另一個是以RISC (Reduced Instruction Set Computing)為基礎的CPU,搭配DSP整合的SOC(System On Chip)為硬體平台,才是我們的選擇。由於這兩種處理器工作性質不相同,我們透過排程工作的演算過程來解決平行處理的工作派任,與不同以往都是先把排程確定後,系統就以固定模式去決定哪些工作由RISC去執行,哪些再由DSP去執行,而這樣的做法就是會讓某一個晶片一直在執行運算,無法達到分工成效,最常看到就是無法執行多個多媒體運算後,再去執行簡單輸入或輸出的行為,因為整個系統資源都被高運算的處理器占住,於是,我們改變以即時監控資源來判斷任務派工該如何進行,才能讓資源發揮物盡其用的效能表現;另外,不同性質的核心有不同架構,彼此資料傳遞單位也不同,如何減少因這些因素導致通訊困難使效能減緩,此刻,加入記憶體管理元件- DMA (Direct Memory Access),來改善時間消耗在兩個不同處理器間的通訊問題;最後,解決一個運算量最大的多媒體處理技術,提出動態品質控管演算法,主要是提升管理編碼的效能,讓串流播放順暢,透過對系統效能的監視,知道何時可以讓DSP多執行點工作,何時可以減少編碼在DSP運作,才不至於系統資源都被某個運算給拖住。
手持裝置的硬體規劃強調是可長期攜帶去使用,但不諱言的是,多媒體的運用真的越來越廣泛,而它們執行的都是會消耗晶片運算,消耗的能量越多,電量也越成正比去消耗,倘若,電池能量無法變大下,就無法高續航力補給;且在硬體框架無法改變下,因此,我們提出透過軟體的運算來改善效能,進而讓使用者可以使用輕薄的手持裝置執行炫麗多媒體與長效時間執行。
Nowadays the combination of multi-media and handheld devices has become the mainstream consumptive product. Processing of multi-media signals such as video and stream on such devices is more and more frequently. How to realize smooth processing of multi-media signal has become a hot topic. A lot of hardware manufacturers will improve performance by adding more CPUs, while some others make use of use Graphic Processing Unit (GPU) or Digital Signal Processor (DSP) to accelerate graphic processing. In terms of the software, it will manage memory, control the process of programs and simplify the algorithms to achieve the objective of meeting the time requirements. To sum up, the independent processing of software and hardware can’t optimize the performance improvement. Therefore, the dissertation will focus on applying the characteristics of the hardware platform on the handheld devices and integrating with the software management to conduct appropriate performance allocation for the architecture of the multi-media processor.
There are two common methods to improve hardware performance. One is adding more CPU cores, in which the cores process is in a sequential way that makes it more difficult to write the multi-media players on application layer. Thus, we don’t choose such hardware platform. The other is a hardware platform composed of a CPU based on Reduced Instruction Set Computing (RISC) and a System On Chip (SOC) integrated with DSP, which is our choice due to the parallel processing of DSP. With scheduling algorithm, we resolve the assignment of parallel processing tasks for two different processors, which is different from the previous solution that the first makes the schedule and then distributes the tasks for RISC and DSP respectively in a fixed way. In this way, a certain chip will keep computing, so it fails to achieve the effectiveness of task partitioning. The common scenario is they can’t perform multiple multi-media computing tasks before processing the simple input/output, because all system resources are occupied by high-computing processor. In view of this, we change to adjust the time for task assignment by real-time monitoring resources, so as to maximize the performance of the resources. Besides, the core architecture varies in different characteristics, so does the data transmission unit. Regarding reducing the performance degradation due to these factors, Direct Memory Access (DMA) is added to improve the communication problem of time consumed between two different processors. Finally, in order to resolve image compression- the multi-media processing technology with the heaviest computing, the dynamic quality control algorithm is proposed. It mainly improves the encoding performance, achieving smooth stream playing. By monitoring the system performance, it knows when to assign more tasks to DSP, and when to reduce the encoding workload in DSP. Consequently, it avoids the system resources not being occupied by a certain computing.
The highlight of hardware scheme for the handheld device lies in the portability. However, to confess, as the multi-media will be applied more widely and the execution will consume chip computing, the battery power will become less in a proportional way with more energy consumed. If it fails to gain more battery power, it will be unable to achieve high-endurance power supply. Thus, we propose improving performance by software computing, which further allows the user to execute various multi-media in a long time on light and slim handheld devices.
Abstract...................................................................1
中文摘要....................................................................3
Acknowledge................................................................5
Table of Contents...................................................................6
List of Figures...................................................................10
List of Tables....................................................................11
Chapter 1 Introduction..............................................................12
1.1 Motivation…………………………………..……………...........................……………...12
1.2 The proposed optimization approached and their contribuctions.....................................................………....13
1.2.1 Architecture for video coding on processor with an ARM and DSP...................................................................…...13
1.2.2 A video decoding optimization for asymmetric dual-core platform architecture………….................................……………………………………………………………….16
1.2.3 Architecture for video streaming application on heterogeneous.....................................................……......18
1.3 Organization..........................……………………..………………………….………...21
Chapter 2 Architecture for video coding on a processor with an ARM and DSP ..........................................................................23
2.1 System overview.......…...........………........……………………………………………...23
2.2 Asymmetric multi-core processing architecture…….....….…………..……...24
2.3 Internal-processor communication mechanism…………….…........……….....25
2.3.1 Implement processing………………………………….....................………………...25
2.3.1.1 Implement processing for ARM side……..............……………………….….25
2.3.1.2 Implement processing for DSP side…..........……………………...……....26
2.4 Intra prediction processing……….............………..….…………….………….....26
2.5 Interpolation processing………………..............………………………...…..….....31
2.6 Block matching algorithm for motion estimation…....………….….…….....32
2.6.1 Search block by three step search………………..............…………………...33
2.6.2 Comparsion related search block algorithm…….........……………………...34
2.7 Temporal redundancy processing…..……….…………….….............……….....36
2.8 Inter prediction processing………………………………................…………….....41
2.9 How to platform module and task with CPU……..........…………………….....43
Chapter 3 A video decoding optimization for asymmetric dual-core platforms architecture……………………………………………………………..............................………….....46
3.1 A discussion about dual-core processor design….......……….………………..47
3.1.1 Access unit consistency………………..……...…...............…………..……...47
3.1.2 Sequence switching issue…………….…………………..................……….....47
3.1.3 Consistency of data sharing issue………........………………...….……......48
3.2 Asymmetric multi-core decoding architecture…...........……………………..49
3.2.1 Task processing unit………………………………...................………………….....50
3.2.2 Task distributor and task interface….......……………………………...….....51
3.3 H.264 bitstream transcoder………...………………….............…….……….….....51
3.3.1 Spatial downscaling……..………………….................…………….…………......52
3.3.2 Mixed block……………………………………………........................……………......52
3.4 H.264 key frame generator……………….................……………………………......54
3.4.1 Scene change………………………..……………......................…………………......54
3.4.2 Playback control elements………..............……………..……………………......55
3.5 Optimization for DMA architecture……………...........………………...…….....56
3.5.1 Dual-core processing architecture…….........…………………………...….....56
3.5.2 Internal-processor communication mechanism……….....…………...….....58
3.5.2.1 Implement processing for ARM side………………...........……………….....58
3.5.2.2 Implement processing for DSP side…………..........………….………….....58
3.5.3 DMA planning…………………………………….........................………………….....58
3.5.4 Dynamically partitioned H.264 decoder…….........……...…………….....59
3.5.4.1 I frame prediction decoding……….............…………..………………….....60
3.5.4.2 Interpolation processing……………….............………..……….………….....62
3.5.4.3 Temporal redundancy…………………..…..................………….………….....63
3.5.4.4 P frame prediction decoding………….............…………..……………….....65
Chapter 4 Architecture for video streaming application on asymmetric platform…………………………………………………………....................................……………………67
4.1 System overview………………………........................……………………………….....67
4.2 Dynamically adjust encoder parameter….........…………...……………….....67
4.2.1 Architecture description……….................………...…………………….....68
4.2.2 The problems with formulation…………............……...…………………….....70
4.2.3 Proposed algorithm…………………...................………..……………………….....71
Chapter 5 Experimental results and assist……............………….………………………....73
5.1 Introductions…..………………......................………………………………….…..…...73
5.2 Experiment of static task scheduling and dynamic task shceduling comparisons………………………………...……...........................…………..………………..……...74
5.3 Experimental results processed in the I frame…..……...…….………….....75
5.4 Experimental results processed in the P frame…………...………...…….....76
5.5 Experiment on streaming library performance………........…………………....78
5.6 Performance improvement summary of DMA architecture….....………..…..81
5.7 Performance comparisons of benchmarking...…….........……………..………..82
Chapter 6 Conclusions…………………..……..................………….…...……………..…......84
6.1 Conclusions…..……………………….......................…………..…………………..…...84
6.1.1 Architecture for video streaming……...…........……..…………………..…...85
6.1.2 Architecture for video decoding optimization……..….………...…..…...85
Reference…………………..…………………….........................………….…...……………..…......88
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