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研究生:林宗翰
研究生(外文):Zong-Han Lin
論文名稱:注入 MOSFET DC偏壓在Above-Threshold區的注入鎖定除2除頻器設計及LC直接注入鎖定除頻器的Figure of Merit
論文名稱(外文):Design of a Divide-by-2 Injection-Locked Frequency Divider with Injection MOSFET DC-biased in Above-Threshold Region and Figure of Merit of a LC Direct-Injection Injection-Locked Frequency Divider
指導教授:張勝良
指導教授(外文):Sheng-Lyang Jang
口試委員:張勝良
口試委員(外文):Sheng-Lyang Jang
口試日期:2015-07-16
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:102
中文關鍵詞:射頻積體電路頻率合成器鎖相迴路注入鎖定除頻器壓控振盪器
外文關鍵詞:RFICFrequency synthesizerPLLILFDDividerVCO
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在無線通訊系統中,頻率合成器是用來做訊號頻率的升降之用。在頻率合成器電路裡,壓控振盪器與除頻器是重要的核心電路之ㄧ。對壓控振盪器而言,必須提供低相位雜訊的輸出,以避免相鄰雜訊訊號經由混波轉換產生干擾。而振盪器的輸出則經由除頻器來達成降頻的工作,因此,除頻器需具有高頻操作、寬的操作頻寬及低功率消耗。
首先,本論文呈現一個單諧振LC諧振器直接注入鎖定除頻器,此注入鎖定除頻器使用了前級放大串連後端注入混波器的功能。此注入鎖定除頻器呈現以不同偏壓下的FOM來找尋能得到最佳FOM的操作偏壓點與其餘偏壓的比較。考慮輸出功率的最佳FOM閘極偏壓較低於不考慮輸出功率FOM的閘極偏壓。
其次,本論文提出一個寬鎖頻範圍除二注入鎖定除頻器,完成於台積電零點一八微米製程,此除二注入鎖定除頻器使用兩個DC偏壓在遠高於臨界電壓的線性電晶體混波器。再汲極-源極的偏壓0.75V、注入功率為0dBm時除二的鎖頻範圍共為4.2GHz,注入頻率從5.6GHz至9.8GHz,鎖頻範圍百分比為54.5%,功率消耗為6.25mW,晶片面積為1.026 × 0.943 mm2
最後,一個完成於台積電零點一八微米矽鍺製程寬鎖定範圍注入鎖定除二除頻器被提出,此注入鎖定除頻器是以電容交叉耦合振盪器為基礎,藉由控制交互耦合電晶體DC閘極偏壓低於DC汲極偏壓,除二注入鎖定除頻器的鎖定範圍會被改善。在供應電壓1.2V時,除頻器的功率消耗為7.8 mW。在注入功率為0dBm時最大的鎖定範圍是3.02GHz(32.23%),注入頻率從7.86GHz道10.88GHz。
In wireless communication system, frequency synthesizers are used to implement the frequency up/down conversion of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal caused by close interfering tones. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
First, this thesis studies the property of a direct-injection LC-tank injection locked frequency divider (ILFD) with a single-resonant LC resonator. The ILFD uses a pre-amplifier stage in series with a post-injection mixer. The ILFD performance is evaluated at various biases by the internal figure of merits to find an optimal bias for ILFD operation with the best FOM to compare with other ILFDs. The optimal mixer gate bias for FOM to consider the output power is lower than the FOM without the output power.
Secondly, a novel wide locking range divide-by-2 injection-locked frequency divider (ILFD) is proposed in the thesis and was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses two linear transistor mixers with dc biased far above threshold voltage. At the drain-source bias of 0.75 V, and at the incident power of 0 dBm, the locking range of the divide-by-2 is 4.2 GHz for the incident frequency extending from 5.6 GHz to 9.8 GHz, and the locking range percentage is 54.5%. The core power consumption is 6.25 mW. The die area is 1.026 ×0.943 mm2.
Finally, a wide locking range divide-by-2 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD is based on a capacitive cross-coupled oscillator. By controlling the dc gate bias of cross-coupled transistors to below the dc drain voltage, the locking range of the divide-by-2 ILFD has been improved. At the supply voltage of 1.2 V, the core power consumption of the ILFD core is 7.8 mW. At the incident power of 0 dBm,the maximum locking range is 3.02 GHz (32.23%), for the incident frequency extending from 7.86 to 10.88 GHz.
中文摘要 I
Abstract III
誌謝 V
Table of Content VI
Figure of Table VIII
List of Table XII
Chapter 1 Introduction 1
1.1 Research Background 1
1.2 Thesis Organization 4
Chapter 2 Principles and Design Concepts of Voltage-Controlled Oscillators 6
2.1 Introduction 6
2.2 The Oscillator Theory 7
2.2.1 One-Port (Negative Resistance) View 8
2.2.2 Two-Port (Feedback) View 11
2.3 The Classification of Oscillators 13
2.3.1 Ring Oscillators 13
2.3.2 LC-Tank Oscillator 16
2.3.3 Cross-coupled Oscillator 21
2.4 Design Concepts of Voltage-Controlled Oscillator 25
2.4.1 Parameters of a Voltage-Controlled Oscillator 26
2.4.2 Phase Noise in Oscillator 27
2.4.3 Kinds of Noise 35
2.5 RLC-Tank research 38
2.5.1 Quality Factor 39
2.5.2 Resistors 42
2.5.3 Inductor and Transformer 43
2.5.4 Capacitors and Varactors 51
Chapter 3 Principles and Design Concepts of Injection Locking Frequency Divider 58
3.1 Principle of Injection Locked Frequency Divider 59
3.2 Locking Range 61
3.3 Direct ILFD 63
Chapter 4 Figure of Merit of an LC Direct-Injection Injection-Locked Frequency Divider 65
4.1 Introduction 65
4.2 Circuit Design 67
4.3 Measurement Results 70
Chapter 5 A Divide-by-2 Injection-Locked Frequency Divider with Injection MOSFET DC-biased in Above-Threshold Region 77
5.1 Introduction 77
5.2 Circuit Design 79
5.3 Measurement Results 82
Chapter 6 A Divide-by-2 Injection-Locked Frequency Divider Based on Capacitive Cross-Coupled Oscillator 87
6.1 Introduction 87
6.2 Circuit Design 88
6.3 Measurement Results 90
Chapter 7 Conclusion 96
References …………………………………………………………………………98
[1]B. Razavi, “RF Microelectronics”, Upper Saddle River, NJ: Prentice Hall, 1998
[2]N. M.Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
[3]B. Razavi, “Design of Analog CMOS Integrated Circuit”,Mc Graw Hill,2008.
[4]J. Roggers, C. Plett, Radio frequency integrated circuit design, Artech House, 2003.
[5]B. Razavi , Design of Integrated Circuits for Optical Communications”, Mc Graw Hill.
[6]B. Razavi, “Design of Analog CMOS Integrated Circuits”, Mc Graw Hill, 2001.
[7]J. van der Tang, and D. Kasperkovitz, “Oscillator design efficiency: a new figure of merit for oscillator benchmarking,” IEEE International Symposium on Circuit and System (ISCAS), vol. 2, pp. 533-536, May 2000.
[8]J.J. Rael, and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569–572, 2000.
[9]T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[10]D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
[11]A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[12]T. H. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuit, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[13]T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
[14]H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun 1974.
[15]J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[16]A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
[17]P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[18]J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[19]Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[20]J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[21]H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[22]H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[23]M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[24]H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[25]R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[26]P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[27]W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[28]H. Wu, “Signal generation and processing in high-frequency/high-speed
silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[29]R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
[30]I. Kwon and K. Lee, “An integrated low power highly linear 2.4 GHz CMOS receiver front-end based on current amplification and mixing,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 1,pp. 36-38, Jan. 2005.
[31]A. Zolfaghari and B. Razavi, “A low-power 2.4 GHz transmitter/receiver CMOS IC,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 176-183, Feb. 2003.
[32]S.-L. Jang, C. C. Liu and C.-Wei Chung, ” A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., pp. 236-238, April, 2009.
[33] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[34]K. Yamamoto and M. Fujishima, “55GHz CMOS frequency divider with 3.2GHz locking range” ESSCC, pp. 135-138, Aug., 2004.
[35]S.-L. Jang, C.-C. Liu, Y.-H. Liao, and R.-K. Yang, “A wide locking range divide-by-2 LC-tank injection locked frequency divider,” IEEE VLSI-DAT., 2010. pp.87-90.
[36]S. L. Jang, S. H. Huang, C. F. Lee, and M. H. Juang, “ LC-tank Colpitts injection-locked frequency divider with record locking range”, IEEE Microw. Wireless Compon. Lett., vol. 18, pp. 560-562, 2008.
[37]N. Hajamini and M. Yavari, “A ring-type ILFD with locking range of 91% for divide-by-4 and 40% for divide-by-8 with quadrature outputs,” Iranian Conf. Electrical Eng. (ICEE), Iran, May 2013
[38]T. Ohira, ” Extended Adler's injection locked Q factor formula for general one- and two-port active device oscillators,” IEICE Electronics Express, Vol. 7, No.19, 1486–1492. 2010.
[39]B. Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, 39(9):1415-1424, Sept. 2004.
[40]Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006..
[41]S.-L. Jang, L.-y. Tsai and C.-F. Lee, ” A CMOS switched resonator frequency divider tuned by the switch gate bias ,” Microw. Opt. Technol. Lett.,Vol. 50, no. 1, pp.222-225, Jan. 2008.
[42]S.-L. Jang, R.-K. Yang, C.-W. Chang and M.-H. Juang, ” Multi-modulus LC injection-locked frequency dividers using single-ended injection,” IEEE Microw. Wireless Compon. Lett., pp. 311-313, May, 2009.
[43]J.-C. Chien and L.-H. Lu, “40 GHz wide-locking range regenerative frequency divider and low-phase-noise balanced VCO in 0.18 um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 544–545.
[44]S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J. F. Huang" Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., accepted 2014..
[45]S.-L. Jang, F.-B. Lin, and J.-F. Huang, ” Wide-band divide-by-2 injection-locked frequency divider using MOSFET mixers DC-biased in subthreshold region,” Int. J. Circuit Theory and Applications .,2015.
[46]S.-L. Jang, C.-C. Liu and C.-W. Tai, ” Implementation of 6-port 3D transformer in injection-locked frequency divider,” IEEE Int. VLSI- DAT, pp. 223-226, 2009.
[47]Y.-T. Chen, M.-W. Li, T.-H. Huang, and H.-R. Chuang, “A V-band CMOS direct injection-locked frequency divider using forward body bias technology,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 396-398, July. 2010..
[48]Sheng-Lyang Jang, Yu–Tai Chang, Ching-Wen Hsue and Miin-Horng Juang.“Wide-locking range divide-by-4 injection-locked frequency divider using injection MOSFET DC-biased above threshold region” International Journal of Circuit Theory and Applications 7 JUL 2015 DOI: 10.1002/cta.2116
[49]S.-L. Jang and C.-Y. Lin, ” A wide-locking range Class-C injection-locked frequency divider,” Electronics Lett. .,vol. 50, 23, pp.1710-1712, 2014.
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