臺灣博碩士論文加值系統

首先，本論文提出一個三頻帶注入鎖定除三除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎，並加上六階RLC共振腔來實現。此電路在可調電壓下，可以產生三個振盪頻帶與三個鎖頻範圍。在直流汲極源極偏壓在0.9伏特，注入訊號強度為0dBm時，可得三個注入鎖定頻帶分別為8.51~11.98 GHz， 4.92~8.64 GHz 與 4.88~5.93 GHz。我們可以找到一個寬鎖定範圍為4.38~8.82 GHz。此晶片的核心功率消耗為6.759 mW，晶片面積為0.991×1.045 mm2。

其次，我們將相同的除三除頻器使用單端注入訊號。經由控制可變電容對間的電壓，相同地可以產生三個振盪頻帶與三個鎖頻範圍。當注入訊號為0 dBm時，在高、中、低頻的鎖頻範圍分別為8.41~11.46 GHz， 5.40~8.68 GHz 與 4.78~5.77 GHz.。
最後，一個寬鎖定範圍注入鎖定除二除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎，並加上六階RLC共振腔來實現。在直流汲極源極偏壓在0.9伏特，注入訊號強度為0dBm時，可得到最大鎖定範圍5.77GHz，經可變電容對間的開關操作，可得全電路的操作頻帶為2.05~8.76 GHz。此晶片的核心功率消耗為6.76 mW。

First, a triple-band divide-by-3 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-3 ILFD use a cross-coupled nMOS pair and a 6th order RLC resonator with three resonant frequencies. The ILFD has three oscillation frequency bands and three locking ranges, which can be measured at fixed tuning bias and tuning bias. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, 3.47GHz (33.87％) from 8.51 to 11.98 GHz, 3.72GHz (54.86％) from 4.92 to 8.64 GHz and 1.05GHz (19.76％) from 4.88 to 5.93 GHz. The largest locking range is given by 4.43GHz (67.07%) from 4.39 to 8.82 GHz. The core power consumption is 6.759 mW. The die area is 0.991×1.045 mm2.

Secondly, the divide-by-3 ILFD uses a single-ended injection signal, a cross-coupled nMOS pair and an injection MOSFET. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges via varactor control voltage. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, given by 3.05GHz (30.70％) from 8.41 to 11.46 GHz, 3.28GHz (46.59％) from 5.40 to 8.68 GHz and 0.99GHz (18.77％) from 4.78 to 5.77 GHz. The operation range is 6.68GHz, extending from 4.78 to 11.46 GHz.

Finally, a wide-band divide-by-2 LC injection-locked frequency divider was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a cross-coupled nMOS pair and a 6th order RLC resonator. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, the maximum locking range of the divide-by-2 ILFD is 5.77GHz (105.2％) from 2.6 to 8.37 GHz, and the operation range is 6.71GHz (124.14％) from 2.05 to 8.76 GHz via varactor switching. The core power consumption is 6.76 mW.

中文摘要 I
Abstract III
致謝 V
Table of Contents VI
List of Figures IX
List of Tables XVII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Thesis Organization 4
Chapter 2 Overview of the Voltage–Controlled Oscillators 5
2.1 Introduction 6
2.2 Design Parameters of Voltage Controlled Oscillator 7
2.3 Basic Theory of Oscillators 11
2.3.1 One-Port (Negative Resistance) View 12
2.3.2 Two-Port (Feedback) View 15
2.4 Oscillators 17
2.4.1 Ring Oscillator 18
2.4.2 LC-Tank Oscillator 22
2.4.3 Research in RLC Tank 26
2.4.4 Type of the LC Oscillator 29
2.4.4.1 Single Transistor Oscillator 31
2.4.4.2 One-Port Oscillator (Negative-Gm Oscillator) 33
2.4.4.3 Cross-Coupled Oscillator 37
2.4.4.4 Complementary Cross-Coupled Topology 39
2.5 Quality Factor 42
2.6 Phase Noise 43
2.6.1 Definition of Phase Noise 43
2.6.2 Linear Time-Invariant (LTI) Phase Noise Model 44
2.6.3 Linear Time-Variant Phase Noise Model 48
2.6.4 Classification of Noise 51
2.6.4.1 Thermal noise 51
2.6.4.2 Flicker noise 53
2.6.5 Phase Noise in Communications 54
2.6.6 Models of Phase Noise 56
2.6.7 Figure of Merit 56
2.7 Elements of Semiconductor Process 57
2.7.1 Resistor 57
2.7.2 Inductor 58
2.7.3 Transformer 66
2.7.3.1 Planar transformer 68
2.7.3.2 Stacked transformer 69
2.7.4 Capacitor 71
2.7.5 Varactor 73
2.7.5.1 P-N Reverse Biased Diode 73
2.7.5.2 MOS Varactor 75
2.7.5.3 The Accumulation-Mode (A-mode) MOS Capacitor 77
2.7.5.4 The Inversion-Mode (I-mode) MOS Capacitor 78
2.8 Dual-Band Resonator 79
Chapter 3 Concepts and Design of Injection-Locked Frequency Divider 83
3.1 Principle of Injection-Locked Frequency Divider 84
3.2 Locking Range 86
3.3 Direct ILFD 88
Chapter 4 A Triple-band Divide-by-3 Injection-Locked Frequency Divider Using
6th-Order RLC Resonator 90
4.1 Introduction 90
4.2 Circuit Design 91
4.3 Measurement Result 95
Chapter 5 Divide-by-3 Injection-Locked Frequency Divider with Multi-
Resonator 101
5.1 Introduction 101
5.2 Circuit Design 103
5.3 Measurement Result 110
Chapter 6 A Wide-band Divide-by-2 Injection-Locked Frequency Divider Using
6th-Order Resonator 116
6.1 Introduction 116
6.2 Circuit Design 117
6.3 Measurement Result 121
Chapter 7 Conclusion 125
References 127

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