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研究生:鄭惟中
研究生(外文):Wei-Chung Cheng
論文名稱:使用六階RLC共振腔之三頻帶除三注入鎖定除頻器與除二注入鎖定除頻器之設計
論文名稱(外文):Design of Triple-band Divide-by-3 and Divide-by-2 Injection-Locked Frequency Divider Using 6th-Order RLC Resonator
指導教授:張勝良徐敬文
指導教授(外文):Sheng-Lyang JangChing-Wen Hsue
口試委員:張勝良徐敬文
口試委員(外文):Sheng-Lyang JangChing-Wen Hsue
口試日期:2015-07-15
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:133
中文關鍵詞:注入鎖定除頻器除二除三
外文關鍵詞:ILFDDivide-by-2Divide-by-3
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首先,本論文提出一個三頻帶注入鎖定除三除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎,並加上六階RLC共振腔來實現。此電路在可調電壓下,可以產生三個振盪頻帶與三個鎖頻範圍。在直流汲極源極偏壓在0.9伏特,注入訊號強度為0dBm時,可得三個注入鎖定頻帶分別為8.51~11.98 GHz, 4.92~8.64 GHz 與 4.88~5.93 GHz。我們可以找到一個寬鎖定範圍為4.38~8.82 GHz。此晶片的核心功率消耗為6.759 mW,晶片面積為0.991×1.045 mm2。

其次,我們將相同的除三除頻器使用單端注入訊號。經由控制可變電容對間的電壓,相同地可以產生三個振盪頻帶與三個鎖頻範圍。當注入訊號為0 dBm時,在高、中、低頻的鎖頻範圍分別為8.41~11.46 GHz, 5.40~8.68 GHz 與 4.78~5.77 GHz.。
最後,一個寬鎖定範圍注入鎖定除二除頻器被實現在台積電點一八製程。此電路是以交叉耦合的壓控振盪器作為基礎,並加上六階RLC共振腔來實現。在直流汲極源極偏壓在0.9伏特,注入訊號強度為0dBm時,可得到最大鎖定範圍5.77GHz,經可變電容對間的開關操作,可得全電路的操作頻帶為2.05~8.76 GHz。此晶片的核心功率消耗為6.76 mW。
First, a triple-band divide-by-3 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-3 ILFD use a cross-coupled nMOS pair and a 6th order RLC resonator with three resonant frequencies. The ILFD has three oscillation frequency bands and three locking ranges, which can be measured at fixed tuning bias and tuning bias. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, 3.47GHz (33.87%) from 8.51 to 11.98 GHz, 3.72GHz (54.86%) from 4.92 to 8.64 GHz and 1.05GHz (19.76%) from 4.88 to 5.93 GHz. The largest locking range is given by 4.43GHz (67.07%) from 4.39 to 8.82 GHz. The core power consumption is 6.759 mW. The die area is 0.991×1.045 mm2.

Secondly, the divide-by-3 ILFD uses a single-ended injection signal, a cross-coupled nMOS pair and an injection MOSFET. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges via varactor control voltage. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the high-band, middle-band and low-band locking range of the divide-by-3 ILFD are, respectively, given by 3.05GHz (30.70%) from 8.41 to 11.46 GHz, 3.28GHz (46.59%) from 5.40 to 8.68 GHz and 0.99GHz (18.77%) from 4.78 to 5.77 GHz. The operation range is 6.68GHz, extending from 4.78 to 11.46 GHz.

Finally, a wide-band divide-by-2 LC injection-locked frequency divider was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a cross-coupled nMOS pair and a 6th order RLC resonator. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, the maximum locking range of the divide-by-2 ILFD is 5.77GHz (105.2%) from 2.6 to 8.37 GHz, and the operation range is 6.71GHz (124.14%) from 2.05 to 8.76 GHz via varactor switching. The core power consumption is 6.76 mW.
中文摘要 I
Abstract III
致謝 V
Table of Contents VI
List of Figures IX
List of Tables XVII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Thesis Organization 4
Chapter 2 Overview of the Voltage–Controlled Oscillators 5
2.1 Introduction 6
2.2 Design Parameters of Voltage Controlled Oscillator 7
2.3 Basic Theory of Oscillators 11
2.3.1 One-Port (Negative Resistance) View 12
2.3.2 Two-Port (Feedback) View 15
2.4 Oscillators 17
2.4.1 Ring Oscillator 18
2.4.2 LC-Tank Oscillator 22
2.4.3 Research in RLC Tank 26
2.4.4 Type of the LC Oscillator 29
2.4.4.1 Single Transistor Oscillator 31
2.4.4.2 One-Port Oscillator (Negative-Gm Oscillator) 33
2.4.4.3 Cross-Coupled Oscillator 37
2.4.4.4 Complementary Cross-Coupled Topology 39
2.5 Quality Factor 42
2.6 Phase Noise 43
2.6.1 Definition of Phase Noise 43
2.6.2 Linear Time-Invariant (LTI) Phase Noise Model 44
2.6.3 Linear Time-Variant Phase Noise Model 48
2.6.4 Classification of Noise 51
2.6.4.1 Thermal noise 51
2.6.4.2 Flicker noise 53
2.6.5 Phase Noise in Communications 54
2.6.6 Models of Phase Noise 56
2.6.7 Figure of Merit 56
2.7 Elements of Semiconductor Process 57
2.7.1 Resistor 57
2.7.2 Inductor 58
2.7.3 Transformer 66
2.7.3.1 Planar transformer 68
2.7.3.2 Stacked transformer 69
2.7.4 Capacitor 71
2.7.5 Varactor 73
2.7.5.1 P-N Reverse Biased Diode 73
2.7.5.2 MOS Varactor 75
2.7.5.3 The Accumulation-Mode (A-mode) MOS Capacitor 77
2.7.5.4 The Inversion-Mode (I-mode) MOS Capacitor 78
2.8 Dual-Band Resonator 79
Chapter 3 Concepts and Design of Injection-Locked Frequency Divider 83
3.1 Principle of Injection-Locked Frequency Divider 84
3.2 Locking Range 86
3.3 Direct ILFD 88
Chapter 4 A Triple-band Divide-by-3 Injection-Locked Frequency Divider Using
6th-Order RLC Resonator 90
4.1 Introduction 90
4.2 Circuit Design 91
4.3 Measurement Result 95
Chapter 5 Divide-by-3 Injection-Locked Frequency Divider with Multi-
Resonator 101
5.1 Introduction 101
5.2 Circuit Design 103
5.3 Measurement Result 110
Chapter 6 A Wide-band Divide-by-2 Injection-Locked Frequency Divider Using
6th-Order Resonator 116
6.1 Introduction 116
6.2 Circuit Design 117
6.3 Measurement Result 121
Chapter 7 Conclusion 125
References 127
[1]B. Razavi, “RF Microelectronics 2nd edition”, Upper Saddle River, NJ: Prentice Hall, 2010
[2]S. Smith, “Microelectronic Circuit 4th edition” , Oxford University Press 1998.
[3]J. Roggers, C. Plett, “Radio frequency integrated circuit design”, Artech House, 2003
[4]N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators”, IEEE J. Solid-State Circuit, vol. 27, no. 5, pp.810-820, May 1992
[5]B. Razavi, “Design of Integrated Circuits for Optical Communications”, Mc Graw Hill.
[6]S. J. Lee, B. Kim, K. Lee, “A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme”, IEEE Journal of Solid-State Circuits, vol. 32, No. 2, February 1997.
[7]G. Gonzalez, “Microwave Transistor Amplifiers Analysis and Design”, Prentice Hall, 1997
[8]S. H. Lee, S. L. Jang, “Implementation of New High Frequency CMOS VCOs and Injection-Locked Frequency Dividers ”, April 2007.
[9]J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications”, Kluwer Academic Publishers, 2004.
[10]B. De Muer, M. Borremans, M. Steyaert, and G. Li. Puma, “A 2GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization”, IEEE J. Solid-State Circuits, vol. 35, pp.1034-1038, 2000.
[11]S.Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, “Frequency Dependence on Bias Current in 5GHz CMOS VCOs:impact on tuning range and flicker noise upconversion”, IEEE J. Solid-State Circuits, vol. 37, pp.1001-1003, 2002
[12]T. H. Lee, “The Design of CMOS Radio Frequency Integrated Circuits”, Cambridge University Press, 1998
[13]J. Craninckx and M. S. J. Steyaert, “A 1.8 GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736–744, May 1997.
[14]J. J. Kim, B. Kim, “A low-phase-noise CMOS LC oscillators with a Ring Structure,” ISSCC Digest of Technical Papers, pp.430-431, Feb. 2000.
[15]J. Savoj, B. Razavi, High-Speed CMOS Circuits For Optical Receivers, Kluwer Academic Publishers, 2001.
[16]A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE ISSCC Dig. Tech. Papers, pp. 392-393, Feb. 1996.
[17]T. Lee, and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
[18]D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
[19]A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[20]A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
[21]C. P. Yue, C. Ryu, JackLau, T. H. Lee, and S. Wong, “A physical model for planar spiral inductors on silicon,” 1996 International Electron Devices Meeting Technical Digest, pp. 155–158, Dec. 1996
[22]A. Hajimiri, and T. H. Lee, “Design Issues in CMOS differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
[23]A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators, Springer 1999.
[24]J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[25]Marc Tiebout, Low Power VCO Design in CMOS, Springer 2009.
[26]J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[27]Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[28]J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[29]H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[30]H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[31]H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[32]R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOSinjection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[33]P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An injection-locking scheme for precision quadrature generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[34]W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25μm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[35]A. Buonomo and A. Lo Schiavo, Nonlinear dynamics of divide-by-two injection-locked frequency dividers in locked operation mode, Int. J. Circ. Theor. Appl., vol. 42, no. 8, pp. 794–807, 2013.
[36]S.-L. Jang, F.-B. Lin, and J.-F. Huang, wide-band divide-by-2 injection-locked frequency divider using MOSFET mixers DC-biased in subthreshold region, accepted. Int. J. Circ. Theor. Appl..,2014.
[37]Plessas F. A study of superharmonic injection-locking in multiband frequency dividers. Int. J. Circ. Theor. Appl. 39:397–410, 2011.
[38]S. Verma, H. R. Rategh and T. H. Lee, "A unified model for injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol. 38, pp1015-1027, June, 2003.
[39]H. Wu and A. Hajimiri, "A 19GHz, 0.5mW, 0.35um CMOS frequency divider with shunt-peaking locking-range enhancement," IEEE ISSCC Dig. Tech. Papers, pp.412-413, Feb., 2001.
[40]Tiebout M. A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider. IEEE J SolidState Circuits, 2004, 7(39): 1170
[41]S.-L. Jang, C.-W. Chang, J.-Y. Wun, and M.-H. Juang, ” Quadrature injection-locked frequency dividers using dual-resonance resonator,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 1, pp. 37-39, Jan. 2011.
[42]S.-L. Jang, L.-T. Chou, J.-F. Huang, and C.-W. Chang, ” A dual-band dual-resonance quadrature injection-locked frequency divider,” IEICE Trans. Electron., Vol.E94-C,No.8,pp.1336-1339, Aug. 2011.
[43]S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol. 55, 10, pp. 2333–2337, October 2013
[44]S.-L. Jang, R.-K. Yang, C.-W. Chang, M.-H. Juang, and C.-C. Liu, ” Dual-band transformer-coupled quadrature injection-locked frequency dividers,” Microw. Opt. Technol. Lett., pp.1561-1564, July, 2011.
[45]S.-L. Jang, C.-C. Shih, C.-C. Liu, and M.-H. Juang, ” CMOS injection-locked frequency divider with two series-LC resonators,” Microw. Opt. Technol. Lett., pp.290-293, Feb., 2011.
[46]L. Wu and H. C. Luong, "Analysis and design of a 0.6V 2.2 mW 58.5-to-72.9 GHz divide-by-4 injection-locked frequency divider with harmonic boosting," IEEE Trans. Circuits Syst. I, Regular Papers, vol. 60, no. 8, pp. 2001-2008, Aug. 2013.
[47]H.Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp.27–29.
[48]S.-L. ang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
[49]S.-L. ang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, July, 2010.
[50]S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned injection-locked frequency divider,” Analog Integr Circ Sig Process, Vol. 76, 1, pp. 111-116., Jan. 2013.
[51]Y.-T. Chen., M.-W. Li, H.-C. Kuo, T.-H. Huang, and Chuang H.-R. : “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–67, 2012.
[52]S.-L. Jang and J.-H Hsieh, ” A wide-locking range ÷3 injection-locked frequency divider using concurrent injection mechanisms,” Analog Integr Circ Sig Process., Vol. 77, pp 593-598, 2013
[53]S.-L. Jang, C.-Y. Lin, and M.-H. Juang, ” Enhanced locking range technique for a divide-by-3 differential injection-locked Frequency divider,” Electron. Lett., vol. 51, 19, pp. 456 – 458, 2015.
[54]S.-L. Jang, and C.-Y. Lin,” A wide-locking range Class-C injection-locked frequency divider,” Electron. Lett., vol. 50, 23, pp.1710-1712, 2014.
[55]J. Jeong and Y. Kwon, “A fully integrated V-band PLL MMIC using 0.15um GaAs pHEMT technology,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp.1042-1050, May. 2006.
[56]J. Jeong, S. Kim, W. Choi, H. Noh, K. Lee, K.-S. Seo, and Y. Kwon, "W-band divide-by-3 frequency divider using 0.1 μm InAlAs/InGaAs metamorphic HEMT technology," Electron. Lett., pp. 1005 – 1006, Sep.2005
[57]S.-L. Jang, W. Yeh, C.-F. Lee, and M.-H. Juang” A low power CMOS divide-by-3 LC-tank Injection-Locked frequency divider ,” Microw. Opt. Technol. Lett.,Vol. 50, no. 1, pp.259-262, Jan. 2008.
[58]S.-L. Jang, R.-K. Yang, C.-W. Chang and M.-H. Juang, ” Multi-modulus LC injection-locked frequency dividers using single-ended injection,” IEEE Microw. Wireless Compon. Lett., pp. 311-313, May, 2009.
[59]S.-L. Jang, C.-F. Lee and W.H. Yeh, ” A divide-by-3 Injection-Locked frequency divider with single-ended input,” IEEE Microw. Wireless Compon. Lett., pp. 142-144, Feb. 2008.
[60]S.-L. Jang, J.-C. Luo, C.-W. Chang, C.-F. Lee and J.-F. Huang, ” LC-tank Colpitts injection-locked frequency divider with even and odd modulo,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 2, pp. 113-115, Feb. 2009.
[61]X. Yi, C. C. Boon, M. A. Do, K. S. Yeo, and W. M. Lim, “Design of ring-oscillator-based injection-locked frequency dividers with single-phase inputs”, IEEE Microw. Wireless Compon. Lett., vol. 21, no. 10, 559 - 561, Oct. 2011.
[62]B. Razavi, "A study of injection-locking and pulling in oscillators," IEEE J. Solid-State Circuits, 39(9):1415-1424, Sept. 2004.
[63]Wu J.-W, C.-C. Chen, H.-W. Kao, J.-K. Chen, and M.-C. Tu,”Divide-by-three injection-locked frequency divider combined with divide-by-two locking,” IEEE Microw. Wireless Compon. Lett., pp. 590-592, Nov.,2013.
[64]C.-F. Lee and S.-L. Jang,,” A low voltage divide-by-3 injection-locked frequency divider,” Microw. Opt. Technol. Lett., pp. 1905-1908, July, 2008
[65]P.-K. Tsai, C.-Y. Liu, T.-H. Huang, and J.-W. Wu, “K-Band, low-power CMOS injection-locked divide-by-three circuit using shunt-peaking and current-bleeding techniques,” Microw. Opt. Technol. Lett., vol. 54, no. 3, pp. 577-579, Mar. 2012.
[66]Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
[67]H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[68]S. Lee, S. Jang, and C. Nguyen, “Low-power-consumption wide-locking-range dual-injection-locked 1/2 divider through simultaneous optimization of VCO loaded Q and current,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 10, pp. 3161–3168, Oct. 2012.
[69]C.-W. Chang, S.-L. Jang, C.-W. Huang, and C.-C. Shih, " Dual-resonance LC-tank frequency divider implemented with switched varactor bias,” IEEE Int. VLSI- DAT, 2011, pp.1-4.
[70]S.-L. Jang and T.-C. Fu, " Effects of hot-carrier stress on the RF performance of a 0.18μm MOS divide-by-4 LC injection-locked frequency divider," Fluct. Noise Lett. 13, No. 2, 1450009 (2014).
[71]J.-F. Huang, S.-L. Jang, W.-Ch. Liu, and M.-H. Juang, ” Over-voltage stressed dual-resonance injection-locked frequency divider with series-peaking injection device,” Analog Integr Circ Sig Process., 81, pp.789-795, 2014.
[72]Y. Tsividis, "Operation and Modeling of the MOS Transistor," New York: Oxford University Press, 2008.
[73]S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
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1. 江斌玉(1997),〈激勵行為與績效研究〉,《銘傳學報》,24期,頁81-109。
2. 賴怡瑩(2005),〈人事人員之角色變遷及核心能力〉,《人事月刊》,第40卷第2期,頁63。
3. 賴怡瑩(2005),〈人事人員之角色變遷及核心能力〉,《人事月刊》,第40卷第2期,頁63。
4. 蔡祈賢(2006),〈值得推展的-員工協助方案〉,《人事月刊》,第42卷第1期,頁20-28。
5. 蔡祈賢(2006),〈值得推展的-員工協助方案〉,《人事月刊》,第42卷第1期,頁20-28。
6. 劉光華(1997),〈人事人員應有之新觀念新作法〉,《人事月刊》,第42卷第5期,頁36-43。
7. 劉光華(1997),〈人事人員應有之新觀念新作法〉,《人事月刊》,第42卷第5期,頁36-43。
8. 陳金貴、呂育誠(2006),〈我國人事人員管理制度變革之研究〉,《公務人員月刊》,第125期,頁5-15。
9. 陳金貴、呂育誠(2006),〈我國人事人員管理制度變革之研究〉,《公務人員月刊》,第125期,頁5-15。
10. 曹有培(1987),〈我國大專體育教師工作滿意度及其影響因素之研究〉,《中華民國體育學會體育學報》,第15期,頁213-232。
11. 曹有培(1987),〈我國大專體育教師工作滿意度及其影響因素之研究〉,《中華民國體育學會體育學報》,第15期,頁213-232。
12. 林聰男(2008),《地方制度法施行後縣市政府人事制度之變革及未來發展趨勢》,人事月刊,第273期,頁37-41。
13. 林聰男(2008),《地方制度法施行後縣市政府人事制度之變革及未來發展趨勢》,人事月刊,第273期,頁37-41。
14. 呂育誠(2008),《全球化對我國地方公務人力管理的意涵與展望》,人事月刊,第273期,頁12-23。
15. 呂育誠(2008),《全球化對我國地方公務人力管理的意涵與展望》,人事月刊,第273期,頁12-23。