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研究生:葉士豪
研究生(外文):Shih-Hao Yeh
論文名稱:基於Synopsys合成工具對QDI電路面積和耗電分析與研究
論文名稱(外文):AREA AND POWER CONSUMPTION ANALYSIS OF QDI CIRCUITS BASED ON SYNOPSYS SYNTHESIS TOOL
指導教授:鄭福炯鄭福炯引用關係
指導教授(外文):Fu-Chiung Cheng
口試委員:鄭福炯
口試委員(外文):Fu-Chiung Cheng
口試日期:2015-01-29
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:68
中文關鍵詞:XNOR閘XOR閘準延遲漠然
外文關鍵詞:XNORXORQDI
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本論文針對同步電路與非同步電路進行有無使用XOR對電路的面積及耗能的差異,基於ISCAS-85的例子,使用Design compiler並且用Synopsys的G-tech library來限制17種的排列邏輯組合並對每一個例子去分析所使用的邏輯閘數量,再使用fast library來分析面積和耗能。
成本和面積的優化對於電路設計是一個很重要的考量,在同步電路裡面若使用XOR閘可以降低邏輯閘的使用數量,但是XOR閘的面積成本比起其他邏輯閘要大得多,根據非同步電路的分析可以發現NCLD電路每種邏輯閘的成本是相等的,所以在非同步電路成本相同的情況下使用XOR閘會比同步電路有更好的效果。ISCAS-85中c1355的例子比較使用XOR閘和一般2-input電路效果是最好的,邏輯閘個數少了1.34倍,NCLD面積成本則是少了1.33倍,印證了邏輯閘數目與同步電路邏輯閘數目會是相等的。QDI電路成本比較面積成本以NCLD為基準1倍,NCLX與ROC分別比NCLD省2.17倍和2.8倍,耗能成本則是以NCLX為基準1倍,NCLD與ROC分別比NCLX省1.27倍和2.66倍。
In this paper, presence or absence of differences in the use of XOR circuit area and power consumption for synchronous and asynchronous circuits, based on ISCAS-85 for example, by using Synopsys Design compiler and the G-tech library to arrange a logical combination of 17 kinds of restrictions and for each example to analyze the number of logic gates used, then use the fast library to analyze the area and power consumption.
Costs and optimize the area of the circuit design is a very important consideration, if use the synchronization circuit which can reduce the number of XOR gate using logic gates, but the area of cost XOR gate logic gate is much greater than the other, according to the analysis of asynchronous circuits can be found in each logic gate circuit NCLD costs are equal and so the use of asynchronous circuits in the same situation XOR gate will cost have better results than synchronous circuits. ISCAS-85 in comparative examples c1355 using XOR gates and the general effect of 2-input circuit is the best, 1.34 times the number of logic gates less, NCLD area is 1.33 times less cost, and confirms the number of logical gates and synchronization circuit the number of logic gates will be equal.
致謝 1
摘要 2
ABSTRACT 3
目錄 4
圖目錄 6
表目錄 8
Chapter 1 簡介 10
1.1 動機及問題描述 10
1.2 論文貢獻 12
1.3 論文架構 12
Chapter 2 知識背景 14
2.1 同步與非同步電路 14
2.2 非同步電路信號通訊協定 16
2.3 非同步電路資料編碼 18
2.3.1 Bundled data 18
2.3.2 Dual-rail data 19
2.4 QDI組合電路 19
2.4.1 NCLD QDI非同步電路 20
2.4.2 NCLX QDI非同步電路 21
2.4.3 ROC QDI非同步電路 22
2.4.4 ISCAS-85電路介紹 23
Chapter 3 相關研究 31
3.1 傳統的邏輯合成 31
3.1.1 典型的兩級(two-level)布林函數 31
3.1.2 Exclusive Sum-of-Product 32
Chapter 4 實驗方法與分析 34
4.1 實驗方法 34
4.1.1 Design compiler去限制邏輯閘的組合 34
4.1.2 Fast.db Library做電路分析 35
4.2 同步與非同步電路分析 37
4.2.1 XOR對於同步電路影響 38
4.2.2 XOR對於非同步電路的影響 39
4.3 實驗流程 42
Chapter 5 實驗結果分析 48
5.1 同步電路評估 48
5.2 非同步電路評估 50
5.2.1 QDI非同步電路- XOR閘比較 51
5.2.2 QDI電路在FPGA邏輯個數 55
Chapter 6 結論 58
參考文獻 59
附錄一 61
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