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研究生:林宥任
研究生(外文):You-Ren Lin
論文名稱:可程式化除頻器內高速低功耗預除器的研究
論文名稱(外文):The Study of High-Speed Low-Power Prescaler in Programmable Frequency Divider
指導教授:林明郎
指導教授(外文):Ming‐Lang Lin
口試委員:林明郎
口試委員(外文):Ming‐Lang Lin
口試日期:2015-07-17
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:71
中文關鍵詞:預除器功率消耗除頻器
外文關鍵詞:power consumptionfrequency dividerprescaler
相關次數:
  • 被引用被引用:0
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  • 收藏至我的研究室書目清單書目收藏:0
在降低功率消耗的技術上,常藉由減少電晶體的數量來降低負載電容來達成目的,本論文也以此技術為基礎提出一個不同的架構來降低功率的消耗。其中主要提出一個可關閉的ETSPC-DFF電路,此電路可在雙模式(÷N/N+1)預除器處於÷N的模式下將其關閉,藉此有效的降低功率消耗。本論文的除頻器架構是可程式化的,由預除器、兩個計數器和一個控制信號產生器組成的。而預除器的功率消耗大約占整體除頻器的90%,藉由降低預除器的功率消耗來達到目的。本論文使用TSMC 0.18 µm製程,最大操作頻率可到4.3GHz,最多可以降低大約26%的功率消耗。
The technology to reduce the power consumption of the divider is often by reducing the number of transistors used in circuits. Based on this technology, a switchable ETSPC-DFF circuit is proposed to effectively reduce power consumption. When the dual mode (÷N/N+1) prescaler in ÷N mode, the switchable ETSPC-DFF will be turned off. The architecture of frequency dividers used in this thesis is programmable and composed of a prescaler, two counters and a control signal generator. The prescaler consumes about 90% overall power. The technology of reducing the power consumption of the prescaler can be used to achieve the power saving. TSMC 0.18 μm process technology is adopted in this thesis, the maximum operating frequency is up to 4.3GHz, and about 26% power saving.
致謝 II
摘要 III
Abstract IV
目錄 V
圖目錄 VII
表目錄 X
第1章 緒論 11
1.1 頻率合成器介紹 11
1.2 研究動機與論文架構 13
第2章 除頻器介紹 14
2.1 除頻器方塊圖 14
2.2 除頻器結構單元 16
2.2.1 雙模式預除器 16
2.2.2 可程式化計數器 18
2.2.3 MC信號產生器 21
第3章 預除器介紹 24
3.1 TSPC與ETSPC差異 24
3.1.1 操作原理 24
3.1.2 操作速度 26
3.1.3 功率消耗 28
3.2 可關閉的ETSPC-DFF 31
3.3 各種模式預除器 34
3.3.1 除2/3預除器 34
3.3.2 除4/5預除器 37
3.3.3 除8/9預除器 40
3.4 預除器比較 46
3.4.1 使用除2/3預除器組成的除64/65除頻器 46
3.4.2 使用除4/5預除器組成的64/65除頻器 48
第4章 模擬驗證 52
4.1 HSpice電路設計模擬 53
4.1.1 固定除數改變P、S配置 53
4.1.2 固定P值,改變S 58
4.2 電路佈局後的電路模擬 60
4.2.1 固定除數改變P、S配置 61
4.2.2 Post-sim 固定P值,改變S 63
第5章 結論 68
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[2]W.-H. Chen, B.-Jung, "High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers," IEEE Transactions on Circuits and Systems, vol.58, no.3, pp.144,148, March 2011
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[6] Z. Gao et al. "A programmable high-speed pulse swallow divide-by-N frequency divider for PLL frequency synthesizer," International Conference on Computer Application and System Modeling , vol.6, no., pp.V6-315,V6-318, 22-24 Oct. 2010
doi: 10.1109/ICCASM.2010.5619385
[7] Y.-H. Peng, and L.-H. Lu, "A 16-GHz Triple-Modulus Phase -Switching Prescaler and Its Application to a 15-GHz Frequency Synthesizer in 0.18- \mu m CMOS," IEEE Transactions on Microwave Theory and Techniques , vol.55, no.1, pp.44,51, Jan. 2007
[8] Krishnapura, N.; Kinget, P.R., "A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS," IEEE Journal of Solid-State Circuits, vol.35, no.7, pp.1019,1024, July 2000
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[10] T.-S. Jau, W.-B. Yang, Yu-Lung Lo, "A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler," Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on , vol., no., pp.902,905, 10-13 Dec. 2006
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