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研究生:曾美禎
研究生(外文):Chen-Mei Tseng
論文名稱:相鄰互斥或運算FDR測試資料壓縮
論文名稱(外文):Neighboring XOR FDR Test Data Compression
指導教授:曾王道
指導教授(外文):Wang-Dauh Tseng
口試委員:陳勇志陳聰明
口試委員(外文):Yong-chi ChenNext-Clever Chen
口試日期:103-11-28
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:103
語文別:中文
論文頁數:27
中文關鍵詞:積體電路(IC)FDR壓縮率比較游程編碼
外文關鍵詞:Integrated circuit (IC)FDR compression ratio comparisonRLE
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電子系統廣泛被應用于我們生活的各個角落,而電子系統的關鍵是積體電路(IC)板。近二十幾年來,隨著造大規模積體電路(VLSI)技術的迅速發展,晶片中的電晶體的數量倍數增加,積體電路測試日益成為一個挑戰。為了要節省測試資料和測試時間,壓縮測試資料是一個常見且有效率的方法。本論文是頻率導向運行長度資料編碼法(Frequency-Directed Run-length coding)為架構,發展出新的壓縮方法以提昇壓縮效能。
Electronic systems are widely used in various corners of our lives, and the key electronic system is an integrated circuit (IC) boards. The past 20 years, with the rapid development of large-scale integrated circuit manufacturing (VLSI) technology, the number of multiple wafer crystals increases, integrated circuit testing is increasingly becoming a challenge. In order to save the test data and test time, test data compression is a common and efficient way. This paper is staggered run-length data coding method (Frequency-Directed Run-length coding) for the architecture, the development of new compression methods to improve compression quality.
目錄
書 項 名 I
論文口試委員審書 II
中文摘要 III
英文摘要 IV
誌 謝 V
目 錄 VI
表 目 錄 VII
圖 目 錄 VIII

第一章、簡介 1
1.1研究介紹 1
1.2研究目的與架構 3
第二章、研究目的與架構. 4
2.1相關研究 4
2.2研究動機與想法 13
第三章、方法. 14
3.1方法流程 14
3.2方法說明 16
第四章、編碼方法還原之硬體架構. 19
第五章、實驗結果. 21
第六章、結 論. 24
參考資料 25


[1] A. Chandra and K. Chakrabarty , “Frequency-directed runlength (FDR) codes with application to system-on-a-chip test data compression ,” in Proceedings of the 19th IEEE VLSI Test symposium(VTS’01),PP.42-47,Marina Del Rey , Calif , USA, March2001.

[2] J. Feng and G. Li , “A test data compression method for system-on-a-chip , ” in proceedings of the 4th IEEE International Symposium on Electronic Design , Test and Applications (DELTA’08) , Hong Kong , January 2008.

[3] A. H. EI-Maleh, S. S. Khursheed , and S. M. Ssit , “Efficient static compaction
techniques for sequential circuits based on reverse-order restoration and test
relaxation, ”IEEE Transactions on Computer Aided Design of Integrated Circuit s
and Systems , vo1.25 , no.11 pp.2556-2564 , 2006.

[4] A. Chandra and K. Chakrabarty , “Test data compression and test resource
partitioning for system-on-a-chip using frequency-directed run-length
(FDR)codes ,” IEEE Transactions on Computers , VO1.52,NO.8 , PP. 1076-1088,
2003.

[5] H. Fang , C. Tong, and X. Cheng , “Run Based Reordering : a novel approach for test data compression and scan power,” in Proceedings of the Conference on Asia South Pacific Design Automation (ASP-DAC ’07) , Yokohama , Japan, January 2007.

[6] G. Sheng , et al ., “Combined partial test vector reuse and FDR coding for two dimensional So C test compression ,” in Proceedings of the International Conference onInternet Computing in Science and Engineering (ICICSE ’08) , Harbin , China , January 2008.
[7] W. Zhan , H. Liang, F. Shi , et al ., “Test data compression scheme based on variable-to-fixed-plus-variable-length coding,” Journal of Systems Architecture , vol. 53 , no.11, pp. 877–888 , 2007.

[8] A.H. El-Maleh and R.H. Al-Abaji , “Extended Frequency-Directed Run Length
Code with Improved Application to System-on-a-Chip Test Data
Compression , ”Proc. 9th IEEE Int. Conf. Electron ., Circuits Syst ., 2002 , P. 449.

[9] Usha S.Mehta , Kankar S. Dasgupta , NiranjanM. Devashrayee ,“Run-Length Test
Data Compression Techniques : How Far from Entropy and Power Bounds?—ASurvey , ” 2010 VLSI Design , Jan.2010.

[10] P.T. Gonciari , B. Al-Hashimi, and N. Nicolici , “Improving Compression Ratio , Area Overhead , and Test Application Time for System-on-a-Chip Test Data Compression/Decompression ,” Proc. Design Autom. Test Europe , Paris , 2002,P. 604.

[11] P. Gonciari , B. Al-Hashimi, and N. Nicolici , “Variablelength input Huffman coding for system-on-a-chip test ,” IEEE Transactions on Computer-Aided Design , vol. 22, no. 6 , pp.783–796 , 2003.

[12] A. El-Maleh and R. Al-Abaji , “Extended frequency-directed run-length code with improved application to system-on-achip test data compression ,” in Proceedings of the 8th IEEE International Conference on Electronic Circuits and Systems (ICECS ’02) , vol. 2, pp. 449–452 , Dubrovnik, Croatia , September 2002.
[13] A. Jas et al., “An Efficient Test Vector Compression Scheme Using Selective Huffman Coding ,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22 , no. 6 , 2003,
[14] El-Maleh, A ., and Al-Suwaiyan , A.: "An efficient test relaxation technique for
combinational and full-scan sequential circuits" Proc. VLSI Test Symp.,
Monterey , CA , April 2002 , pp. 53-59.

[15] C. Giri , B Rao , and S , Chattopadhyay , ”Test data compression by spilt-VIHC(SVIHC) , ”in Proceedings of the international Conference on Computing: Theory and Applications (ICCTA’07) , Kolkata , India , March 2007.

[16] A. Nourani and M.H. Tehranipour , “RL-Huffman Encoding for Test Compression and power Reduction in Scan Applications ,” ACM Trans. Design Automation of Electronics Systems, vo1. 10 , pp.91-115 , Jan.2005.

[17] X. Ruan and R. Katti ,” Data=independent pattern run=length compression for testing embedded cores in SoCs ,”IEEE Transactions on Computers , vo1.56 , no.4 , pp.545-556 ,2007.

[18] Chloupek , M , Novak , O ,”Test pattern compression based on pattern overlapping and broadcasting ,” in10th International Workshop on Electronics , Control, Measurement and Procelngs(ECMS) , June 2011.
[19] Bo YE , Min Luo ,“A New Test Data Compression Method for System-on-a-
Chip ,”Computer Science and Information Technology (ICCSIT) , pp. 129 –133 , Shanghai , China , July 2010 .

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