電子系統廣泛被應用于我們生活的各個角落，而電子系統的關鍵是積體電路（IC）板。近二十幾年來，隨著造大規模積體電路（VLSI）技術的迅速發展，晶片中的電晶體的數量倍數增加，積體電路測試日益成為一個挑戰。為了要節省測試資料和測試時間，壓縮測試資料是一個常見且有效率的方法。本論文是頻率導向運行長度資料編碼法（Frequency-Directed Run-length coding）為架構，發展出新的壓縮方法以提昇壓縮效能。

Electronic systems are widely used in various corners of our lives, and the key electronic system is an integrated circuit (IC) boards. The past 20 years, with the rapid development of large-scale integrated circuit manufacturing (VLSI) technology, the number of multiple wafer crystals increases, integrated circuit testing is increasingly becoming a challenge. In order to save the test data and test time, test data compression is a common and efficient way. This paper is staggered run-length data coding method (Frequency-Directed Run-length coding) for the architecture, the development of new compression methods to improve compression quality.

目錄
書 項 名 I
論文口試委員審書 II
中文摘要 III
英文摘要 IV
誌 謝 V
目 錄 VI
表 目 錄 VII
圖 目 錄 VIII

第一章、簡介 1
1.1研究介紹 1
1.2研究目的與架構 3
第二章、研究目的與架構. 4
2.1相關研究 4
2.2研究動機與想法 13
第三章、方法. 14
3.1方法流程 14
3.2方法說明 16
第四章、編碼方法還原之硬體架構. 19
第五章、實驗結果. 21
第六章、結 論. 24
參考資料 25

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