本論文實現了一個特定短距通訊收發機中頻電路的帶通濾波器。相較於濾波器相關文獻，該電路具有小電路面積、與低功率消耗的優點。為了工作在不同製程飄移與操作環境變異，該帶通濾波器系統增加了一可自我進行校正迴路。
所提出的帶通濾波器採用主動電感與電晶體電容組成的諧振式負載，經小訊號模型電路分析與模擬完成帶通特性的驗證。該帶通濾波器具有3個參數來分別調整增益與導通頻帶 (1)輸入反相器之轉導，(2) 主動電感值與電容值，(3) 正迴授反相器的轉導。此外，帶通特性也藉由串接多級帶通濾波器來加強。接著透過0.18微米CMOS製程，我們實現了一串接6級並有外部7位元導通頻帶控制信號的帶通濾波器測試晶片。帶通濾波器本身耗費0.16mm2的晶片面積，測試結果顯示導通頻帶可藉由數位控制從27MHz調整至41MHz，距離增益峰值頻率40MHz有2.5MHz頻寬的相鄰通道有16dB的增益衰減，整個電路操作在1.8V的供應電壓下有14.8mW的功率消耗。
導通頻帶自我校正迴路包含迴路峰值檢測器、取樣-保持電路、峰值比較器、信心計數器、峰值追鎖控制器與導通頻帶控制有限狀態機。在峰值檢測器中加入輸入緩衝電路以避免信號的直流飄移誤差並提升峰值檢測器的增益與線性操作範圍。在峰值追鎖控制器實現一導通頻帶追蹤機制與判斷是否完成追蹤。該自我校正系統用0.18微米CMOS製程實現晶片佈局並耗費0.18mm2的面積，佈局後模擬結果顯示當校正迴路操作在312.5kHz時脈下，系統可於使48μs的時間(10個時脈週期)內完成40MHz導通頻帶的校正。

This thesis realizes a band-pass-filter (BPF) for the intermediate-frequency (IF) circuit of the decidated-short-range-communication (DSRC) transceiver. Compare to the reported BPF designs, this thesis with a smaller circuit area and a lower power consumption. In order to compensate the process and operational condition variation, the proposed BPF adds a pass-band calibration feedback loop.
The proposed BPF uses resonant loads consisted of active inductors and MOS varactor array to make good band-pass filtering characteristics. Small signal model of the resonant loads are analyzed and are verified by HSPICE simulation. Four BPF parameters are utilized for the performance adjustment: the transconductance of input inverter, the transconductance of positive feedback inverter, the inductance of active inductor and the capacitance of MOS varactor. In addition, band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged from 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 402.5MHz. The input third-order intercept point is 6dbm.
The pass-band calibration feedback loop include a Peak detect, a sample and hold circuit, a Peak voltage comparator, a confidence counter, a peak tracking controller (PTC) and a Pass- band control finite state machine (PC FSM). In the peak detector, we propose an input buffer to cancel the offset error and to raise the gain and the linear operation range. In PTC, a low-hardware overhead pass-band tracking mechanism and a lock detection mechanism are proposed. In 0.18um CMOS technology, the calibration circuit occupies an active area of 0.18mm2. The post layout simulation results reveal that the locking time is about 48us with a 40MHz of target pass-band frequency and a 312.5kHz of reference clock.

書名頁 i
論文口試委員審定書 ii
論文授權書 iii
中文摘要 iv
英文摘要 vi
誌謝 viii
目錄 ix
圖目錄 xi
表目錄 xv
第一章、緒 論 1
1.1 研究動機 1
1.2 論文組織 4
第二章、帶通濾波器背景知識 5
2.1 濾波器轉移函式 6
2.2 轉導式帶通濾波器簡介 8
2.3 迴轉器(Gyrators)式主動電感[14] 9
2.4 濾波器校正系統相關文獻 12
2.5 總結 20
第三章、數位控制帶通濾波器 21
3.1 數位可調濾波器之設計 23
3.2 電路模擬結果 27
3.3 測試電路板設計與量測環境設置及量測結果 30
第四章、導通頻帶自我校正迴路設計 34
4.1 導通頻帶校正迴路系統架構 34
4.2 校正迴路分部模組1 : 峰值檢測器(Peak Detector) 36
4.3 校正迴路分部模組2 :信心計數器 (Confidence Counter) 52
4.4 校正迴路分部模組3 :峰值追索控制器 (Peak tracking controller)與鎖定偵測器(也就是所謂的turn counter) 56
4.5 校正迴路分部模組4 :導通頻帶控制有限狀態機 (Passband Control FSM) 58
4.6 自我校正迴路之系統模擬 61
第五章、具自我導通帶校正迴路之帶通濾波器晶片實作 63
5.1 晶片架構與佈局 63
5.2 模擬結果 69
5.3 總結 71
第六章、結論與未來工作 72
6.1 結論 72
6.2 未來工作1: 帶通濾波器與導通頻帶自我校正迴路量測 74
6.3 未來工作2: 未來改進工作動機與提出方式 77
參考文獻 80

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