(3.236.118.225) 您好!臺灣時間:2021/05/17 09:24
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:朱維正
研究生(外文):Wei-Chung Chu
論文名稱:負電容電晶體之模擬研究
論文名稱(外文):A Simulation Study for Negative Capacitance Field Effect Transistor
指導教授:張書通湯銘
口試委員:李昌駿
口試日期:2016-06-23
學位類別:碩士
校院名稱:國立中興大學
系所名稱:光電工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:78
中文關鍵詞:鐵電負電容次臨界擺幅
外文關鍵詞:FENCSSUTB-DGFinFETNanowireHZO
相關次數:
  • 被引用被引用:0
  • 點閱點閱:78
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著元件微縮達到物理極限,鐵電負電容這項概念將是一個能突破現況的轉捩點,目前此領域不管是UC Berkeley的S. Salahuddin教授或Fraunhofer Center的Johannes Müller等專家都已推廣鐵電負電容概念。
室溫下的MOSFET之Boltzmann tyranny物理極限2.3kbT/decade限制了開關特性斜率,堆疊鐵電層(FE) 作為具有負電容(NC)效應之介電層提供低開啟電壓。為了驗證NC的概念可將body factor (m)<1,利用Landau model模擬NC效應並建立其理論模型。然而,負電容效應中最具代表性的電滯迴圈會因鐵電層厚度而產生電滯現象,此現象對於製作記憶體很重要;但是為了應用在CMOS操作上,電滯現象就會成為元件性能上缺點,所以需要找到能不產生電滯現象且具有最小次臨界擺幅(SS)的最佳鐵電層厚度才能達到陡峭斜率電晶體。鐵電負電容目前被廣泛運用成NCFET並證實其有效性,而為了使電性臻於完美,傳輸機制(n factor)也是另外一項可改善的參數,搭配ultra-thin body與double gate成為UTB-DG-NCFET能使SS明顯下降。
另外,模擬鐵電負電容的應用在現有電晶體技術FinFET和次世代電晶體技術Nanowire的可能性,將會是本論文研究的重點之一。



Abstract
The concept of ferroelectric negative capacitance could be a turning point to break through the state-of-the-art with scaling-down to reach physical limitation. Currently, authority in this field whether Prof. S. Salahuddin in UC Berkeley''s or Johannes Müller in Fraunhofer Center and other experts have promoted the concept of a ferroelectric negative capacitance for a period of time.

Physical limitation of Boltzmann tyranny with 2.3kbT/decade for MOSFET at room temperature restricts the switching slope. Integrated ferroelectric (FE) as dielectric with negative capacitance (NC) effect provides low-operation-voltage. To demonstrate the concept of negative capacitance(body factor (m) <1), the simulation of NC Effects were used by Landau model to build the theoretical model. However, hysteresis loop would cause phenomenon of hysteresis by thickness of ferroelectric layer. The effect of hyseresis is very important to memory fabrication. In order to applicate CMOS, this effect will be a defect in the devices’ performance. So we should find the optimized thickness of ferroelectric layer with hysteresis-free and lowest Subthreshold Swing(SS) to achieve steep slope transistor. Ferroelectric negative capacitance have been widely used and proven its validity for NCFET. For reaching ideal state, transport mechanism (n factor) is another parameter to improve. With ultra-thin body, double gate(UTB-DG) ,it bring out UTB-DG-NCFET that can obviously decrease SS.

In addition, a simulation study for the possibility of negative ferroelectric capacitor used in the prior transistor technology ‘FinFET’ and the next-generation transistor technology ‘Nanowire’ will be one focus of this thesis.








目錄
致謝辭....................................................VI
中文摘要.................................................VII
英文摘要.................................................VIII
目錄......................................................IX
圖目錄...................................................XII
表目錄..................................................XVII

第一章 緒論............................................1

第二章 文獻回顧與論文導讀
2-1負電容元件的可能性與模擬文獻............................3
2-2三維鰭式鐵電負電容電晶體實作元件文獻...................13

第三章 運用表面電位計算鐵電效應
3-1 HZO的polarization....................................19
3-2 Gibb’s free energy和surface potential...............20
3-3 計算流程..............................................23
3-4 NC元件之功率消耗......................................24
第四章 鐵電負電容改善電性的基礎概念和評斷方式
鐵電負電容電場反饋........................................25

第五章 HZO鐵電負電容場效電晶體(MOSFET)
5-1 研究動機...............................................29
5-2模擬方法與元件結構.....................................30
5-3 模擬結果...............................................31

第六章 Fitting HZO鐵電負電容場效電晶體
(Epi Ge /Si MOS)實驗數據
6-1 研究動機與模擬方法與元件結構..........................35
6-2 模擬與fitting結果....................................36

第七章 超薄基板雙閘極鐵電負電容場效電晶體元件設計及優化
7-1 研究動機...............................................38
7-2元件模擬方法與設計.....................................40
7-3不同結構對電晶體特性之影響
7-3-1不同元件尺寸的電子密度分佈圖.....................41
7-3-2不同鐵電層厚度對電晶體特性之影響.................45
7-3-3不同基板厚度對電晶體特性之影響...................47
7-3-4不同介面層厚度對電晶體特性之影響.................50
7-4 UTB-DG-NCFET的結果與討論..............................53

第八章 三維鰭式鐵電負電容場效電晶體元件設計及優化
8-1 研究動機與模擬方法.....................................54
8-2元件設計和Stress.......................................55
8-3不同功函數對電晶體特性之影響...........................58
8-4 NCFinFET的結果與討論..................................68

第九章 未來工作......................................69

參考文獻................................................73

附錄.....................................................76






參考文獻
[1] International Technology Roadmap for Semiconductors (ITRS)
Roadmap, 2009.
[2] G. A. Salvatore, D. Bouvet, and A. M. Ionescu, “Demonstration of
Subthrehold Swing Smaller Than 60mV/decade in Fe-FET with
P(VDF-TrFE)/SiO2 Gate Stack, ” in IEDM Tech. Dig., pp.
167-170, 2008.
[3] A. Rusu, G. A. Salvatore, D. Jimenez, and A. M. Ionescu,
‘‘Metal-Ferroelectric-Metal-Oxide-Semiconductor Field Effect
Transistor with Sub-60mV/decade Subthreshold Swing and Internal
Voltage Amplification,’’ in IEDM Tech. Dig., pp. 395-398, 2010.
[4] S. Salahuddin, and S. Datta, ‘‘Can the subthreshold swing in a
classical FET be lowered below 60 mV/decade, ’’ in IEDM Tech.
Dig., pp. 693-696, 2008.
[5] A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric
Negative Capacitance MOSFET: Capacitance Tuning &
Antiferroelectric Operation, ” in IEDM Tech. Dig., pp. 255-258,
2011.
[6] S. Salahuddin and S. Datta, “Use of Negative Capacitance to
ProvideVoltage Amplification for Low PowerNanoscale Devices, ’’
Nano Lett., Vol. 8, No. 2, pp. 405-410, 2008.
[7] David Jiménez, Enrique Miranda, and Andrés Godoy, “Analytic
Model for the Surface Potential and Drain Current in Negative
Capacitance Field-Effect Transistors, ’’ IEEE Trans. on Electron
Device, vol. 57, no.10, pp. 2405-2409, 2010.
[8] A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric
Negative Capacitance MOSFET: Capacitance Tuning &
Antiferroelectric Operation, ” in IEDM Tech. Dig., pp. 255-258,
2011.
[9] A. I. Khan, D. Bhowmik, P. Yu, S. J. Kim, X. Pan, R. Ramesh and S.
Salahuddin, “Experimental evidence of ferroelectric negative
capacitance in nanoscale heterostructures,’’ Appl. Phys. Lett., Vol.
99, 113501, 2011.
[10] C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin, and C. Hu,
“Low Power Negative Capacitance FETs for Future Quantum-Well
Body Technology, ’’ in VLSI-TSA, pp. 179-180, 2013.
[11] Kai-Shin Li1, Pin-Guang Chen2, 3, Tung-Yan Lai1, Chang-Hsien
Lin1, Cheng-Chih Cheng3, Chun-Chi Chen1, Yun-Jie Wei1,Yun-Fang Hou1, Ming-Han Liao2, Min-Hung Lee3, Min-Cheng Chen1, Jia-Min Sheih1, Wen-Kuan Yeh1, Fu-Liang Yang4,Sayeef Salahuddin5, Chenming Hu5, “Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis, ’’ in IEDM15- pp. 620-623, 2016.
[12] M. H. Lee1, P.-G. Chen1,2, C. Liu3, K.-T. Chen4, M.-J. Xie1,
S.-N. Liu1, H.-H. Chen1, C.-H. Tang1, J.-W. Lee1, W.-H. Tu5,
K.-S. Li6, M.-C. Chen6, M.-H. Liao2, C.-Y. Chang7,8, C.-H. Cheng9, S. T. Chang4, and C. W. Liu5, “Experimental Demonstration of Negative Capacitance epi-Ge/Si FETs with Ferroelectric Hf-based Oxide Gate Stack for Swing Sub-60mV/dec and Hysteresis-Free.’’
[13] L. D. Landau, and I. M. Khalatnikov, “On the anomalous
absorption of sound near a second order phase transition point., ’’
Dokl. Akad. Nauk 1954, 96, 469-472.
[14] V. C. Lo, “Simulation of thickness effect in thin ferroelectric films
using Landau-Khalatnikov theory, ’’ J. Appl. Phys. 2003, 93 (5),
3353-3359.
[15] W. Zhang, and K. Bhattacharya, “A computational model of
ferroelectric domains. Part I: model formulation and domain
switching, ’’ Acta Mater. 2005, 53, 185-198.
[16] Three-dimensional Device Simulations of 10 nm FinFETs Using
Monte Carlo Model and Drift-Diffusion Model With Ballistic
Mobility, TCAD Sentaurus Version H-2013.03.
[17] Chunsheng Jiang1, Renrong Liang1, Jing Wang1, and Jun Xu1,
“A Carrier-Based Analytic Theory for Electrical Simulation of
Negative Capacitance Surrounding Gate Ferroelectric Capacitor,’’ in
Proceedings of the 15th IEEE International Conference on
Nanotechnology July 27-30, pp. 834-837, 2015.






QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top