(3.236.214.19) 您好!臺灣時間:2021/05/10 06:28
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:趙伯頴
研究生(外文):Boy-Yiing Jaw
論文名稱:交錯耦合式電荷泵浦與電壓調節器分析與設計
論文名稱(外文):Analysis and Design of Cross Coupled Charge Pumps and Voltage Regulators
指導教授:林泓均
口試委員:鍾秋嬌林維亮張振豪劉堂傑陳育鑽
口試日期:2016-07-19
學位類別:博士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:英文
論文頁數:78
中文關鍵詞:電荷泵浦電壓調節器
外文關鍵詞:Charge PumpVoltage Regulator
相關次數:
  • 被引用被引用:0
  • 點閱點閱:111
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:28
  • 收藏至我的研究室書目清單書目收藏:0
電荷泵浦電路廣泛應用於非揮發性記憶體、LCD驅動電路、微機電系統與能量收集電路等。電荷泵浦電路串接數級電荷泵浦單元以提高輸入的直流供應電壓。為了設計良好的電荷泵浦電路,我們期望電荷泵浦具有高效率、精確的調節電壓與低輸出漣波的特性。
在本論文中,我們提出具有中位階電壓準位的特殊時脈,並可應用於PMOS電荷泵浦的輸出級以減少輸出漣波。此具有特殊時脈的電荷泵浦使用0.35 μm CMOS製程製作,面積為0.182mm2。高電壓增益與高驅動電流能力之特性也得以維持。
傳統的輸出漣波模型在基於電晶體的導通電阻為零的假設之下,並不能精確預估電荷泵浦的輸出漣波。本論文提出的輸出漣波模型可應用於具有交錯耦合式PMOS輸出級的電荷泵浦,由於將電晶體的導通電阻列入考量,根據輸出漣波模型所計算的結果接近模擬與量測的結果。基於此模型,本論文提出的設計方法可幫助設計者設計高功率效率與低漣波的電荷泵浦。
本論文提出時脈頻率與負載電流相關的電荷泵浦電壓調節器,並且以0.18 μm CMOS製程製作,可得到良好的負載調節率以提升輸出電壓的精確度。藉由控制電晶體的導通電阻,得以調節輸出電壓。此電壓調節器使用感測放大器偵測電荷泵浦內部節點的電壓,調整相對應的切換頻率以提升低負載電流條件下的效率。由於負載偵測電路並非於輸出節點取樣,相較於現存的文獻,此電壓調節器具有更優越的負載調節率,同時廣負載電流範圍下的效率也得以維持。


The charge pump (CP) circuit has been widely used in non-volatile memories, LCD drivers, MEMs, energy harvesting circuits, and so on. The CP circuit cascades several stages of CP units to obtain high boosted DC supply voltages. To design good CP circuits, it is desired to have the CPs with high power efficiency, accurate regulated pumped voltages and low output ripples.
In this dissertation, we propose a special clock scheme with a medium voltage level that can be applied to the output stage of a PMOS CP to reduce output ripples. The CP with the special clock scheme was fabricated using the 0.35 μm CMOS technology on an area of 0.182 mm2. High voltage gain and driving capacity are preserved with the proposed clock scheme.
The conventional output ripple models based on the assumption of zero turn-on resistance of the switching transistors cannot accurately estimate the output ripple of CPs. Since the proposed models of ripples in the CPs with cross-coupled PMOS output stages take into account the accurate turn-on resistance, the calculated results are close to those from simulations and measurements. The design methodology based on the models are proposed to help designers design power-efficient and low ripple CPs.
To enhance the accuracy of pumped output voltage with good load regulation, a CP-based voltage regulator with load dependent clock frequencies is proposed and was fabricated in a standard 0.18-μm CMOS process. The output voltage is regulated by controlling the turn-on resistances of switching transistors. The power efficiencies are improved at light load by detecting the voltages in the interior nodes of CP using sense amplifiers. The switching frequencies are adjusted accordingly. Since the load detection is not sampled at the output, the load regulation is superior to the existing literatures and the power efficiencies are maintained in wide range of loading current.


List of Contents
Acknowledgment i
摘 要 ii
Abstract iii
List of Contents v
List of Tables vii
List of Figures viii
Chapter 1 Introduction 1
1.1 Overviews of Charge Pump Circuits 1
1.2 Overviews of Analytical Models for Charge Pumps 6
1.3 Overviews of Charge Pump Voltage Regulators 6
1.4 Objectives and Organizations 13
Chapter 2 Reduced-Ripple PMOS Charge Pump Circuit with Small Filtering Capacitance 15
2.1 Clock Scheme for Ripple Reduction 15
2.2 Clock Generation Circuits 18
2.3 Simulation and Measurement Results 19
2.4 Summary 24
Chapter 3 Analytical Models of Output Ripples in Charge Pumps with Cross-Coupled Output Stages 25
3.1 Analytical Models of Output Ripples 25
3.2 Extended Models for the Reduced-Ripple Charge Pumps 30
3.2.1 Modeling ripple voltage Vro during Interval T1 32
3.2.2 Modeling ripple voltage Vro during Interval T2 34
3.3 Model Validation and Discussion 35
3.4 Design Methodology 42
3.5 Summary 47
Chapter 4 An Power-Efficient Charge Pump Voltage Regulator with Good Load Regulation 48
4.1 Discussion of Existing Switch Capacitor Regulator 48
4.2 Proposed Control Methods 51
4.2.1 Pumping Current Control for Output Voltage Regulation 53
4.2.2 Pumping Frequency Control for Enhancing Power Efficiency 54
4.3 Implementation of the CP Voltage Regulator 56
4.3.1 PMOS Charge Pump and Auxiliary Clock Circuits 56
4.3.2 Current Detection Circuits 61
4.3.3 Drivers for the Second Stage of the PMOS CP 67
4.4 Simulation and Measurement Results 67
4.5 Summary 71
Chapter 5 Conclusions 72
References 74
List of Publications 78
Journal Papers 78
Conference Papers 78
Patents 78


[1]J. Dickson, “On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. SC-11, no. 3, pp. 374–378, Mar. 1976.
[2]X. Zhang and H. Lee, “An efficiency-enhanced auto-reconfigurable 2x/3x SC charge pump for transcutaneous power transmission,” IEEE J. Solid-State Circuits,vol. 45, no. 9, pp. 1906-1922, Sept.2010.
[3]D. Ma and F. Luo, “Robust multiple-phase switched-capacitor DC-DC power converter with digital interleaving regulation scheme,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 6, pp. 611–619, Jun. 2008.
[4]S. Lufei and K. Hofmann, “Fully integratable 4-phase charge pump architecture for high voltage applications,” in Proc. Int. Conf. Mixed Design of Integrated Circuits and Systems, May 2012, pp. 265-268.
[5]H. Peng, N. Tang, Y. Yang, and D. Heo, “CMOS startup charge pump with body bias and backward control for energy harvesting step-up converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 6,pp. 1618-1628, June 2014.
[6]X. Zhang and H. Lee, “Gain-enhanced monolithic charge pump with simultaneous dynamic gate and substrate control,” IEEE Trans. Very Large Scale Integr. (VlSI) Syst., vol. 21, no. 3, pp. 593–596, Mar. 2013.
[7]S. Tanakamaru and K. Takeuchi, “A 0.5 V operation VTH loss compensated DRAM word-line booster circuit for ultra-low power VLSI systems,” IEEE J. Solid-State Circuits, vol. 46, no. 10,pp. 2406-2415, Oct. 2011.
[8]E. Racape and J.-M. Daga, “A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process,” in Proc. IEEE Eur. Conf. Solid-State Circuits, Sep. 2005, pp. 77–80.
[9]C. P. Hsu and H. Lin, “Enhanced p-channel metal-oxide-semiconductor field-effect transistor charge pump for low voltage applications,” Jpn. J. Appl. Phys., vol.49, pp.04DE16-1-04DE16-6, April 2010.
[10]B. -Y. Jaw and H. Lin, “Reduced-ripple p-channel metal-oxide-semiconductor field-effect transistor charge pump circuit with small filtering capacitance,” Jpn. J. Appl. Phys., vol.51, pp. 02BE09-1-02BE09-5, Feb. 2012.
[11]F. Bedeschi, C. Boffino, E. Bonizzoni, O. Khouri, G. Pollaccia, C. Resta, and G. Torelli, “A low-ripple voltage tripler,” in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 2753-2756.
[12]M. Huang, L. Okamura, and T. Yoshihara, “Charge sharing clock scheme for high efficiency double charge pump circuit,” in Proc. IEEE Int. Conf. Solid-State and Integrated Circuit Technology, Nov. 2010, pp. 248-250.
[13]M. Huang, Y. Zhang, H. Zhang, and T. Yoshihara, “Double charge pump circuit with triple charge sharing clock scheme,” in Proc. IEEE Int. Conf.ASIC,Oct.2011, pp. 128-132.
[14]M. Chen, X. Wu Xiaobo, and M. Zhao, “Novel high efficiency low ripple charge pump using variable frequency modulation,” in Proc. Int. Conf. Microelectronics, Dec. 2010, pp. 228–231.
[15]G. Palumbo, D. Pappalardo, and M. Gaibotti, “Charge-pump circuits: Power-consumption optimization,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 11, pp. 1535–1542, Nov. 2002.
[16]C. P. Hsu and H. Lin, “Analytical models of output voltages and power efficiencies for multistage charge pumps,” IEEE Trans. Power Electron., vol.25, no.6, pp.1375-1385, June 2010.
[17]O.-Y. Wong, H. Wong, W.-S. Tam, and C.-W. Kok, “Dynamic analysis of two-phase switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., vol. 29, no. 1, pp. 302–317, Jan. 2014.
[18]A. Kushnerov, “A seminumerical transient analysis of switched capacitor converters,” IEEE J. Emerging Sel. Topics Power Electron., vol. 2, no. 4, pp. 814-820, Dec. 2014.
[19]T. Tanzawa, “An optimum design for integrated switched-capacitor Dickson charge pump multipliers with area power balance,” IEEE Trans. Power Electron., vol. 29, no. 2, pp. 534-538, Feb. 2014.
[20]B. -Y. Jaw and H. Lin, “An analysis of output ripples for PMOS charge pumps and design methodology,” in Proc. IEEE APCCAS, Dec. 2012, pp. 424-427.
[21]J.-Y. Lee, S. Kim, S. Song, J. Kim, S. Kim, and H. Yoo, “A regulated charge pump with small ripple voltage and fast start-up,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 425-432, Feb. 2006.
[22]B. R. Gregoire, “A compact switched-capacitor regulated charge pump power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944-1953, Aug. 2006.
[23]C.-H. Wu and C.-L. Chen, “A low-ripple charge pump with continuous pumping current control,” in Proc. IEEE Int. 51st Midwest Symp. Circuits Syst., Aug. 2008, pp. 722-725.
[24]H. Lee and P. Mok, “An SC voltage doubler with pseudo-continuous output regulation using a three-stage switchable opamp,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1216–1229, Jun. 2007.
[25]F. Su, W.-H. Ki, and C.-Y. Tsui, “Regulated switched-capacitor doubler with interleaving control for continuous output regulation,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1112–1120, Apr. 2009.
[26]W.-C. Chen, D.-L. Ming, Y.-P. Su, Y.-H. Lee, and K.-H. Chen, “A wide load range and high efficiency switched-capacitor DC-DC converter with pseudo-clock controlled load-dependent frequency,” IEEE Trans. Circuits Syst. I, vol. 61, no. 3, pp. 911–921, Mar. 2014.
[27]A. Saiz-Vela, P. Miribel-Catala, J. Colomer, and J. Samitier, “Low-ripple skipping-based regulation system for a two-phase voltage doubler charge pump,” in Proc. IEEE 52nd Int. Midwest Symp. Circuits and Systems (MWSCAS), Aug. 2009, pp.933–936.
[28]H.-K. Kwan, D. C. W. Ng, and V. W. K. So, “Design and analysis of dual-mode digital-control step-up switched-capacitor power converter with pulse-skipping and numerically controlled oscillator-based frequency modulation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 11, pp. 2132–2140, Nov. 2013.
[29]H. Lee, Z. Hua, and X. Zhang, “A reconfigurable 2×/2.5×/3×/4× SC DC–DC regulator with fixed on-time control for transcutaneous power transmission,” IEEE Trans. Very Large Scale Integr. (VlSI) Syst., vol. 23, no. 4, pp. 712–722, Apr. 2015.
[30]A. Cabrini, A. Fantini, and G. Torelli, “High-efficiency regulator for on-chip charge pump voltage elevators,” Electron. Lett., vol. 42, no.17, pp. 972-973, Aug. 2006.
[31]T.-H. Tsai, B.-Y. Shiu, and B.-H. Song, “A self-sustaining integrated CMOS regulator for solar and HF RFID energy harvesting systems,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 3, pp. 434–442, Sept. 2014.
[32]A. Kalanti, M. Yucetas, J. Salomaa, L. Aaltonen, K. Halonen, “Charge-pump based frequency regulator for precision supply generation,” in Proc. IEEE Int. Symp. Circuits Syst., May 2010, pp. 4077-4080.
[33]Y.-C. Shih and B. P. Otis, “An inductorless DC-DC converter for energy harvesting with a 1.2-?W bandgap-referenced output controller,” IEEE Trans. Circuits Syst. II, vol. 58, pp. 832–836, Dec. 2011.
[34]W. Jung, S. Oh, S. Bang, Y. Lee, D. Sylvester, and D. Blaauw, “A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2014, pp. 398–399.
[35]J. Salomaa, M. Pulkkinen, and K. Halonen, “A switched-capacitor voltage regulator for ultra-low power energy harvesting systems,” in Proc. IEEE 57th Int. Midwest Symp. Circuits and Systems (MWSCAS), Aug. 2014, pp. 45–48.
[36]J. Salomaa, M. Pulkkinen, T. Haapala, M. Nurmi, and K. Halonen, “Power management system for ultra-low power energy harvesting applications,” in Proc. IEEE Int. Symp. Circuits Syst., May 2015, pp. 1086–1089.
[37]S. Wang, M. Huang, Y. Zhang, and T. Yoshihara, “A high efficiency charge pump with continuous frequency charge sharing scheme,” in 2013 IEEE Int. Conf. on Consumer Electronics -China (ICCE-China 2013), Apr. 2013, pp. 45–50.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔