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[1] OpenCores, http://opencores.org/ [2] Ching-Hsiang Chuang, System level Software Simulation for Hardware Implementation and its Incremental Verification with Application to H.264 Main Profile Decoder, master thesis, NCKU, 2007 [3] Yi-Li Lin, Versatile PC/FPGA Based Verification/Fast Prototyping Platform with Application to H.264/AVC 1-Frame Encoder, master thesis, NCKU, 2004 [4] Chun-Wei Lin, Baton Control Unit IP core specification [5] Chun-Wei Lin, DDR3_BUS IP core specification [6] Chun-Wei Lin, DDR3_Interface IP core specification [7] OR1200 Rev 1, http://opencores.org/openrisc,file,b3IxMjAwLXJlbDEudGFyLmJ6Mg [8] Chun-Wei Lin, External Interrupt Generator IP core specification [9] Wishbone Bus Rev 2, http://opencores.org/download,wb_conmax [10] OpenCores, UART 16550 IP core specification [11] Chun-Wei Lin, ram_top IP core specification
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