臺灣博碩士論文加值系統

本論文針對可攜式產品應用，實現一個除了外掛的濾波器外，全晶片化的數位控制的降壓型電源轉換器，並且使用堆疊式功率電晶體的技巧，可以使用標準製程實現可應用於鋰電池(Li-ion battery)輸入電壓範圍(2.7V~4.2V)，輸出電壓為1V，而不會超過本論文使用的製程─TSMC 0.18-μm 1P6M的耐壓上限。此外本論文提出與其他使用堆疊式功率電晶體論文不同的偏壓/驅動方式，使電源轉換器在重載或鋰電池輸入電壓較低的情況時的導通損耗降低，提升電源轉換器系統效率並延長可攜式產品的使用時間。另外為了達到快速驗證混合訊號電路的正確性，在模擬數位電源轉換器的時候將複雜的類比-數位轉換器電路簡化成Verilog-A模型，使模擬時可以跳脫電晶體層級的複雜計算。此方法將可以加速未來設計複雜的數位控制時，驗證數位RTL code正確性的時間不會被類比-數位轉換器拖累。
晶片量測時的負載電流範圍為100mA~500mA，電源轉換器在全抽負載電流範圍都為連續電流模式。從量測結果顯示本論文實現的數位降壓轉換晶片可以操作在輸入電壓為2.7V~4.2V的情況，可以證明提出的堆疊式功率電晶體的驅動方式有正常工作，並且可以改善重載時或鋰電池輸入電壓較低時的系統效率。

In this thesis, we accomplished a fully integrated digitally controlled buck dc-dc converter for portable devices application, The chip was manufactured by TSMC 0.18-μm 1P6M which has two different nominal operation voltage of MOS component, 1.8V and 3.3V, however our work targeted at portable devices, so we realized a buck converter which can tolerant li-ion battery as input voltage (2.7V~4.2V) by using cascode power MOS technique. Moreover, we proposed a novel method to drive and bias the cascode power MOS which is different from other previous work, this technique can improve power converter efficiency, especially when power converter is under heavier load or at lower li-ion battery input voltage, so this method can extend operating time of portable devices. To verify the mixed signal circuit simulation result as fast as possible, in our work, we replace the transistor level circuit of analog to digital converter by Verilog-A behavior model, Verilog-A behavior model can reduce the simulation time due to complicated nonlinear effect of transistor model calculation.
The chip in our work is manufactured by TSMC 0.18-μm 1P6M, and operates in continue current mode form 100mA to 500mA load current, and it can tolerant the li-ion battery as input voltage (2.7V~4.2V) by using cascode power MOS technique. Output voltage of this power converter chip is 1V, peak efficiency is 87.41% when input voltage is 3.3V and load current is 150mA, The conduction loss of proposed driving technique for cascode power MOS was lower than other previous work which is proved by measurement result.

摘要 III
Abstract IV
誌謝 VIII
目錄 IX
表目錄 XI
圖目錄 XII
第一章 緒論 1
1.1.研究動機 1
1.2.目標與貢獻 3
1.3.論文架構簡介 4
第二章 數位降壓型電源轉換晶片系統 5
2.1.系統架構工作原理 5
2.2.數位控制器 11
2.2.1.數位補償器(Digital compensator) 11
2.2.2.數位脈波寬度調變器(Digital pulse-width modulator, DPWM) 12
2.3.類比-數位轉換器(Analog to digital converter, ADC) 15
2.3.1.設計考量與架構選擇 15
2.3.2. SAR 類比-數位轉換器 20
2.4.功率電晶體及驅動電路 21
第三章 操作於鋰電池輸入電壓之功率電晶體 25
3.1.低壓堆疊功率電晶體 28
3.2.常見之堆疊驅動方式 32
3.3.新型堆疊驅動電路偏壓原理 42
第四章 應用於鋰電池之數位控制降壓型直流-直流轉換器晶片設計 47
4.1. Nanosim-VCS混階/混訊設計平台及階層式系統設計 49
4.2.數位控制器電路合成及佈局 54
4.3.類比電路設計及佈局 59
4.3.1.堆疊功率電晶體與驅動電路 59
4.3.2.類比-數位轉換器 65
4.4.晶片佈局整合 70
4.5.系統閉迴路模擬與比較 72
第五章 晶片實做與量測驗證 77
5.1.量測規劃與量測環境 77
5.2.量測結果 80
5.2.1.穩態量測 80
5.2.2.暫態量測 81
5.2.3.效率量測 84
5.3.成果比較與討論 85
第六章 結論與展望 87
6.1.總結與貢獻 87
6.2.未來工作與研究方向 87
6.2.1.使用進階的數位控制 87
6.2.2.分時多工類比-數位轉換器 88
6.2.3.建立功率級的行為模型 88
參考文獻 89

[1]Panasonic, “LITHIUM ION BATTERIES, CGA103450A Datasheet. Available: http://www.houseofbatteries.com/documents/CGA103450A.pdf
[2]Texas Instruments, “Digital Power Controllers, UCD3040 Datasheet. Available: http://www.ti.com/product/ucd3040
[3]Intersil, “6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation, ZL2102 Datasheet. Available:
http://www.intersil.com/content/dam/Intersil/documents/zl21/zl2102.pdf
[4]Silicon Vision, “SIVI-DCBU18V1A, Available:
http://www.si-vision.com/files/SVI-DCBU18V1A.pdf
[5]R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell: Kluwer Academic Publishers, 2001.
[6]A. Prodic and D. Maksimovic, “Design and Implementation of a Digital PWM Controller for a High-Frequency Switching DC-DC Power Converter, in Proc. IEEE Industrial Electronics Conf., vol.2, pp. 893-898, 2001.
[7]A. Prodic and D. Maksimovic, “Design of a digital PID regulator based on look-up tables for control of high-frequency DC-DC converters, in Proc. IEEE Power Electronics Spec. Conf., pp. 18-22, 2002.
[8]A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse width modulator architectures, in Proc. IEEE Power Electronics Specialists Conference, 2004, pp. 4689-4695.
[9]O. Trescases, G. Wei, and W.-T. Ng, “A segmented digital pulse width modulator with self-calibration for low-power SMPS, in Proc. IEEE Electron Devices and Solid-State Circuit Conf., 2005, pp. 367-370.
[10]B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters, IEEE Trans. Power Electronics, vol. 18, no. 1 pp. 438-446, 2003.
[11]H. Peng, A. Prodic, E. Alarcon, and D. Maksimovic, “Modeling of Quantization Effects in Digitally Controlled DC-DC Converters, IEEE Trans. On Power Electronics, vol. 22, no. 1, pp. 208-215, 2007.
[12]Angel V. Peterchev, Jinwen Xiao, and Seth R. Sanders, Member, “Architecture and IC Implementation of a Digital VRM Controller, IEEE Trans. on Power Electronics, vol. 18, no. 1, pp.356-364, Jan. 2003.
[13]Jinwen Xiao, Angel V. Peterchev, Jianhui Zhang, and Seth R. Sanders, “A 4-μA Quiescent-Current Dual-Mode Digitally Controlled Buck Converter IC for Cellular Phone Applications, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2342-2348, Dec. 2004.
[14]Man Pun Chan, and Philip K.T. Mok, “Fully Integrated Digital Controller IC for Buck Converter with a Differential-Sensing ADC, IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 1-4, Dec. 2008.
[15]Sunghwa OK, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, and Chulwoo Kim, “A DC-DC Converter with a Dual VCDL-based ADC and a Self-Calibrated DLL-based Clock Generator for an Energy-Aware EISC Processor, IEEE Custom Integrated Circuits Conference, pp. 551-554, Sept. 2008.
[16]Fuding Ge, Malay Trivedi, William Jiang, and Brent Thomas, “A Multi-Rail hared Error ADC with Pipeline Structure for DC-DC Converter Digital Controller in 0.13μm CMOS Technology IEEE international Midwest Symposium on Circuits and Systems, pp. 25-28, Aug. 2010.
[17]W.-H. Chang, and L.-P. Tai, “Design of a digital power IC, in Proc. IEEE Int. Symp. VLSI Design Automation and Test, pp. 41-44, 2010.
[18]M.-P. Chan, and P. K. T. Mok, “Design and implementation of fully integrated digitally controlled current-mode buck converter, IEEE Trans. on Circuits and Systems I, vol. 58, pp. 1980-1991, Aug. 2011.
[19]Sébastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, and Angelo Nagari, “A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop, IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1546-1556, July 2012.
[20]Huey Chian Foong, Yuanjin Zheng, Yen KhengTan and Meng Tong Tan, “Fast-Transient Integrated Digital DC-DC Converter With Predictive and Feedforward Control, IEEE Trans. on Circuits and Systems I, vol.59, pp. 1567-1576, July 2012.
[21]Justin Shi, Eric Soenen, Alan S. Roth, Ying-Chih Hsu, and Martin Kinyua, Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS, IEEE J. Solid-State Circuits, vol. 47, no.8, pp. 1946-1959, Aug. 2012.
[22]Aleksandar Radic, Zdracko Lukic, Aleksandar Prodic, and Robert H. de Nie, “Minimum-Deviation Digital Controller IC for DC-DC Switch-Mode Power Supplies, IEEE Trans. on Power Electronics, vol. 28, no. 9, pp. 4281-4298, Sep. 2013.
[23]Shangyang Xiao, Weihong Qiu, Greg Miller, Thomax X. Wu, and Issa Batarseh, “An Active Compensator Scheme for Dynamic Voltage Scaling of Voltage Regulators, IEEE Trans. on Power Electronics, vol. 24, no. 1, pp. 307-311, Jan. 2009.
[24]Texas Instruments, “1A, 3MHz Buck Converter with I2C for Dynamic Voltage Scaling, TPS62350 Datasheet. Available: http://www.ti.com/lit/ds/symlink/tps62350.pdf
[25]Intersil, “Multiphase Core Regulator for IMVP-6 Mobile CPUs, ISL6260 Datasheet. Available:
http://www.intersil.com/content/dam/intersil/documents/isl6/isl6260-b.pdf
[26]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, “A 1V 11fj/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18um CMOS, IEEE VLSIC, pp. 241-242, 2010.
[27]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, “A 10-bit 50MS/s SAR ADC With a Monotonic Capacitor Switching Procedure, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
[28]Michiel van Elzakker, Ed van Tuijl, Paul Geraedts, Daniël Schinkel, Eric A. M. Klumperink, and Bram Nauta, “A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1MS/s, IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
[29]A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, no.5 pp. 599-606, May 1999.
[30]Saurav Bandyopadhyay, Yogesh K. Ramadass, and Anantha P. Chandrakasan, “20uA to 100mA DC-DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45nm CMOS, IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2807-2820, Dec. 2011.
[31]Suhwan Kim and Gabriel A. Rincon-Mora, “Efficiency of Switched-inductor DC-DC Converter ICs across Process Technologies, IEEE International Symposium on Circuits and Systems, pp. 460-463, 2012.
[32]Gerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl and Christoph Sandner, Output Stage Topologies of DC-DC Buck Converters Operating up to 5 V Supply Voltage in 65nm CMOS, IEEE Conference on Ph.D. Research in Microelectronics and Rlectronics(PRIME), pp. 105-108, July 2011.
[33]Volkan Kursun, Siva G. Narendra, Vivek K. De, and Eby G. Friedman, HIGH INPUT VOLTAGE STEP-DOWN DC-DC CONVERTERS FOR INTEGRATION IN A LOW VOLTAGE CMOS PROCESS, IEEE International Symposium on Quality Electronic Design, pp. 517-521, 2004.
[34]Jun-Han Choi, Sang-Hui Park, and Gyu-Hyeong Cho,“A Tri-Stack Buck Converter with Gate Coupling Control (GCC) and Quasi Adaptive Dead Time Control (QADTC), IEEE Proceedings of the Custom Integrated Circuits Conference, pp. 1-4, Sept. 2014.
[35]Yongtao Geng, Rajdeep Bondade, and Dongsheng Ma,“High-voltage tolerant power driver with enhanced current drivability for integrated power applications, Analog integrated circuits and signal processing, vol. 79, pp. 469-477, June 2014.
[36]Ahmed Emira, Frank Carr, Hassan Elwan, and Rania H. Mekky, “High Voltage Tolerant Integrated Buck Converter in 65nm 2.5V CMOS, IEEE International Symposium on Circuits and Systems, pp. 2405-2408, May 2009.
[37]Scott K. Reynolds, “A DC-DC Converter for Short-Channel CMOS technologies, IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 111-113, Jan. 1997.
[38]Volkan Kursun, Gerhard Schrom, Vivek K. De, Eby G. Friedman, and Siva G. Narendra, CASCODE BUFFER FOR MONOLITHIC VOLTAGE CONVERSION OPERATING AT HIGH INPUT SUPPLY VOLTAGES, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 464-467, May 2005.
[39]José Rocha, Marcelino Santos, J. M. Dores Costa and Floriberto Lima, “High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies, IEEE ISIE, pp. 775 - 780, Sep. 2007.
[40]José F. da Rocha, Marcelino Santos, J. M. Dores Costa, and Floriberto Lima, 4.2V Tolerant Buck Converter in a Standard 3.3V 0.13μm CMOS Technology, IEEE International Conference on POWERENG, pp. 429-434, Sep. 2007.
[41]José F. da Rocha, Marcelino B. dos Santos, José M. Dores Costa, and Floriberto A. Lima, Level shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter, IEEE Trans. on Industrial Electronics, vol. 55, Sep. 2008.
[42]Chua-Chin Wang, Chih-Lin Chen, Gang-Neng Sung, and Ching-Lin Wang, A high-efficiency DC-DC buck converter for sub-2 x VDD power supply, Microelectronics Journal, vol. 42, issue 5, pp. 709-717, May 2011.
[43]Hyunseok Nam, Youngkook Ahn, and Jeongjin Roh, 5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity, IEEE Trans. on Power Electronics, vol. 27, no. 1, pp. 463-471, Jan. 2012.
[44]Lawrence M. Burns, and David Fisher, “STACKED NMOS DC-TO-DC POWER CONVERSION, U.S. Patent 8,593,128 B2, Nov. 26, 2013.
[45]CIC Referenced Flow for Mixed-signal IC Design, Technical Report, CIC-DSD-ED-08-02, National Chip Implementation Center, Hsinchu, Taiwan, 2008.
[46]林俊賓, Post-Layout Simulation Verification with Nanosim, CIC 訓練課程, 2010.
[47]P. Gang, Behavioral modeling and simulation of analog/mixed-signal systems using Verilog-AMS, in Proc. IEEE Youth Conference on Information, Computing and Telecommunication, pp. 383-386, 2009.
[48]顏祥銘, 應用於電源控管系統的Verilog-A模擬, 財團法人國家實驗研究院國晶片系統設計中心電子報第147期.
[49]Xiongfei Meng, Karim Arabi and Saleh, Novel Decoupling Capacitor Designs for sub-90nm CMOS Technology, IEEE ISQED, 2006.
[50]THOMAS H. LEE, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge University Press, 2003.