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[1]聯華電子,eNVM 嵌入式非揮發性記憶體解決方案。 Web site: http://www.umc.com/chinese/process/g.asp [2]台灣區電機電子工業同業公會,IoT商機滾滾嵌入式記憶體需求暢旺。 Web site: http://www.teema.org.tw/exhibition-detail.aspx?infoid=8418 [3]Ramesh Dewangan, Real Intent Company: Redefining Chip Complexity in the SoC Era, April 3, 2014. Web site: http://www.realintent.com/real-talk/1052/redefining-chip-complexity-in-the-soc-era [4]Kirsch and the Memory Team, “Progress on RRAM as a future Non-Volatine Memory (NVM), SEMATECH, pp. 3-4, 2011. [5]Ch. Hollauer, Shallow Trench Isolation, chapter1.1.2. Web site:http://www.iue.tuwien.ac.at/phd/hollauer/node7.html [6]S. Aritome, et al., A 0.67um2 Self-Aligned Shallow Trench Isolation Cell(SA-STI CELL) for 3V-only 256Mbit NAND EEPROMs, IEEE IEDM Technical Digest, pp. 61-64, 1994. [7]Robert Doering and Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, Second Edition, CRS Press,chapter13, 2008. [8]Hopewell Junction, NY, USA,STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond,The 17th Annual SEMI/IEEE ASMC 2006 Conference, pp. 71-76, 2006. [9]SidanJin, BoronActivationandDiffusionin PolycrystallineSiliconwith Flash-Assist Rapid Thermal Annealing , University OF Florida, 2011. [10]Tuinhout, H., et al. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors. International electron devices meeting. INSTITUTE OF ELECTRICAL & ELECTRONIC ENGINEERS, INC (IEEE), 1997. [11]B. S. Haran, 22 nm Technology Compatible Fully Functional 0.1 μm2 6T-SRAM Cell ,Proc. IEDM, pp. 625-628, 2008. [12]Mann, Randy W., et al. Nonrandom device mismatch considerations in Nanoscale SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20.7 (2012): 1211-1220. [13]Peter J. Geiss, Joseph R. Greco, Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures, IBM USA patent, US6682992 B2, 2004. [14]聯華電子內部訓練教材,快閃記憶體簡介,2015。 [15]Joe.james, SLC vs. MLC: An Analysis of FlashMemory, data manual whitepaper,handbook, pp. 1-5, 2011. [16]Kihwan Choi, Samsung Flash design team, NAND Flash memory ,pp32-33,May7, 2010. Web site: https://www.ece.umd.edu/~blj/CS-590.26/nand-presentation-2010.pdf [17]Jitu J. Makwana, Dr. Dieter K. Schroder,A Non Volatile Memory Overview, chapterII. Web site:http://aplawrence.com/Makwana/nonvolmem.html [18]KLS-Tencor company ,Broadband Brightfield DUV/UV/VIS Inspection. Web site: http://www.kla-tencor.com/Certified-Used-Equipment/2800series.html [19]Applied Materials , SEMVision G3 Defect Review System . Web site: http://gt3i.com/products/applied-materials-semvision-g3-defect-review-system [20]P. Kuo, 2011 seminar of FA house in Hsin-Chu, Failure analsis tool introduction, pp. 2-8, March 2011. [21]JEOL company, JEM-2100F Transmission Electron Microscope . Web site: http://www.jeolusa.com/PRODUCTS/Transmission-Electron-Microscopes-TEM/200-kV/JEM-2100F [22]FEI company, nProber II for Semiconductors. Web site: https://www.fei.com/products/efa/nprober-ii-for-semiconductors/ [23]Tektronix company, 4200-SCS Parameter Analyzer . Web site:http://www.tek.com/4200-scs-parameter-analyzer [24]Porto Alegre, Non-Volatile Memory Emerging Technologies And Their Impacts on Memory System , Pontifici University, Sep 2010.
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