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研究生:林志軒
研究生(外文):Jhih-SyuanLin
論文名稱:應用於無線感測網路之雙取樣超低功耗免外部時脈喚醒接收機
論文名稱(外文):A Reference-Less Ultra-Low Power Wake-Up Receiver with Double-Sampling Technique for Wireless Sensor Networks
指導教授:鄭光偉
指導教授(外文):Kuang-Wei Cheng
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:英文
論文頁數:66
中文關鍵詞:喚醒接收機低功耗通斷鍵控雙取樣包絡偵測閃爍雜訊時脈與資料回復注入鎖定振盪器
外文關鍵詞:Wake-up receiverlow poweron/off keyingdouble-samplingenvelope detection1/f noiseclock and data recoveryinjection-locked oscillator
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本論文提出一個超低功耗通斷鍵控喚醒接收機架構,由於雙取樣技術和射頻增益級的被動放大,操作頻率為24億赫茲,資料速率為200 kbps,供應電壓為1伏特,喚醒接收機的靈敏度達-51.5 dBm,功率消耗為25微瓦,在不需要低雜訊放大器(LNA)、壓控振盪器(VCO)和外部時脈的情況下。
在射頻前端電路裡,利用包絡偵測器把射頻訊號直接降至基頻來取代傳統因壓控振盪器耗電的超外差技術;同樣地,用輸入匹配的被動放大特性來取代耗電的低雜訊放大器;在基頻帶裡,資料經過脈衝產生器(pulse generator)後產生時脈之頻率成分,然後注入時脈與資料回復(CDR)電路的振盪器,此振盪器輸出為位元時脈之頻率與注入訊號頻率相同。
由於閃爍雜訊(1/f noise)與頻率成反比,當射頻訊號直接降至基頻雖然可降低耗電量,卻也因閃爍雜訊的問題使得訊噪比降低,因此本論文想藉由雙取樣技術來移除閃爍雜訊,取樣的時脈不需從外部給,而是由時脈與資料回復電路所產生的位元時脈經過倍頻器後並且對射頻(RF)和中頻(IF)訊號取樣。本喚醒接收機除了外部匹配電路其餘皆完全製作於積體電路且使用90奈米台積電製程,晶片面積為1 × 0.95毫米平方。

This thesis presents an on/off keying wake-up receiver (WuRx) for ultra-low applications. Due to the double-sampling technique and passive amplification of the RF gain stage, the 2.4 GHz WuRx achieves -51.5 dBm sensitivity at 200 kbps while consuming 25 μW from a 1V supply without LNA, VCO and external reference frequency.
The envelope-detection technique is employed to eliminate the power-hungry LO generation in a super-heterodyne receiver. In addition, the passive amplification of the input matching network is employed to remove the power-thirsty LNA. At the baseband, the data is synchronized with the bit clock, which is generated from the clock and data recovery (CDR) circuit. The CDR consists of a clock recovery circuit (CRC) and D flip-flop. The CRC includes an injection-locked oscillator (ILO) and a short pulse generator. The clock is multiplied by 4 for generation of sampling clocks. The sampling clocks are used to sample the RF and IF signals to achieve a double-sampling technique and to remove 1/f noise and offset voltage. The WuRx is fully integrated except an external input matching network. A prototype is fabricated in 90 nm TSMC technology. The chip area is 1 × 0.95 mm2.

List of Figures VI
List of Tables IX
Chapter 1 Introduction 1
1.1 WSN Implementation Requirements 1
1.2 Duty-Cycle Control in Sensors 3
1.3 Wake-Up Receiver Considerations 4
1.3.1 Sensitivity Specification 6
1.3.2 Power Budget 6
1.3.3 Bit Clock 7
1.3.4 Overall Specifications 8
Chapter 2 Wake-Up Receiver System 9
2.1 Modulation Type 9
2.2 Wake-Up Receiver Architectures 9
2.2.1 Super-Heterodyne Architecture 11
2.2.2 Tuned RF (TRF) 11
2.2.3 Sub-Sampling Architecture 12
2.2.4 Double-Sampling Architecture 13
Chapter 3 Receiver Functions and Circuit Designs 15
3.1 Functions of the Receiver 15
3.2 Envelope Detector 19
3.2.1 Conversion Gain Derivation and Design Considerations 21
3.2.2 Feedback Resistors 25
3.2.3 Bandwidth of Proposed ED 27
3.2.4 Input Matching Calculation 27
3.2.5 Sensitivity Calculation 32
3.3 Intermediate Frequency Amplifier 33
3.3.1 Design Consideration 33
3.3.2 Transfer Function of IF Amplifier 34
3.4 Baseband Amplifier 36
3.5 Hysteresis Comparator 37
3.6 Clock and Data Recovery (CDR) Circuit 39
3.6.1 Injection-Locked Mechanism 43
3.6.2 Ring Oscillator 44
3.7 Passive Mixer 46
3.8 Clock Generation and Frequency Multiplier 47
Chapter 4 Measurements 50
4.1 Experimental Setup 50
4.2 Measurement Results 54
Chapter 5 Conclusion and Future Works 62
5.1 Conclusion 62
5.2 Future Works 62
References 64

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