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研究生:李子瑋
研究生(外文):Zih-WeiLi
論文名稱:CMOS毫米波功率放大器及94-GHz CMOS次諧波單混頻器射頻收發機之整合晶片設計研究
論文名稱(外文):CMOS Millimeter-Wave Power Amplifier and 94-GHz CMOS Sub-Harmonic Single-Mixer RF Transceiver
指導教授:莊惠如莊惠如引用關係
指導教授(外文):Huey-Ru Chuang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:84
中文關鍵詞:94-GHzCMOS毫米波功率放大器收發機
外文關鍵詞:94-GHzCMOSmillimeter-wave (MMW)power amplifier (PA)transceiver
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本論文研製CMOS毫米波功率放大器及94-GHz CMOS次諧波單混頻器射頻收發機之整合晶片設計研究,採用TSMC 90-nm GUTM CMOS製程進行設計。使用增益提升技巧之94-GHz CMOS中功率放大器設計上採用串接四級共源極(common source, CS)的疊接(cascode)架構並搭配A類放大器之偏壓形式實現,同時藉由增益提升技巧(gain boosting)的方式使其具有較佳的線性度及功率增益來減輕其它發射機前端電路的設計負擔。使用縮小化3-dB正交耦合器之94-GHz CMOS功率放大器利用TSMC 90-nm GUTM CMOS製程之多層結構特色設計一縮小化耦合器做為功率結合/分波器,用來提升功率放大器之輸出功率以加強發射機系統訊號強度,同時也能改善傳統架構由於面積過大而不利於系統整合的缺點。94-GHz CMOS次諧波單混頻器射頻收發機整合晶片目標為設計一個94-GHz CMOS高增益功率放大器與敝實驗室其它同學設計之射頻收發開關、低雜訊放大器及混頻器進行整合。其發射端及接收端僅採用一個同時具有升頻與降頻功能之混頻器來做使用,中間以收發開關做切換,與傳統架構相比能省下一個混頻器及部份濾波器的使用,進而達到縮小晶片面積的功效,同時也能降低收發機之電路複雜度。電路設計以Agilent ADS與ANSYS 3-D全波電磁模擬軟體HFSS進行模擬,量測部份皆是採用on-wafer方式進行,根據欲量測參數特性之不同,相關量測架設方式亦有所調整。
This thesis presents the research on CMOS millimeter-wave (MMW) medium power amplifiers (PAs) and a 94-GHz CMOS sub-harmonic single-mixer RF transceiver (TRx), implemented by standard TSMC 90-nm GUTM CMOS process. In the 94-GHz CMOS medium power amplifier (MPA) design, a four stage class-A common-source (CS) cascode structure with gain-boosting technique is adopted for linearity and power gain enhancement. In the 94-GHz CMOS balanced PA design, a compact 3-dB miniaturized quadrature coupler is employed as a low-insertion-loss power splitter/combiner to improve the output power and provide an area-efficient solution for balance PA design. In the 94-GHz CMOS single-mixer TRx, a high-gain PA is designed for integrating with T/R switches, a low-noise amplifier (LNA), and a sub-harmonic single up/down conversion mixer. The CMOS TRx uses only one up/down conversion mixer and T/R switches to change the modes between transmitting (Tx) and receiving (Rx) path. Compared with the traditional TRx architecture, it can reduce the chip size without the use of additional mixer and filters, and also simplify the complexity of TRx design. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.
第一章 緒論 1
1.1 研究動機與背景 1
1.2 論文架構 2
第二章 使用增益提升技巧之94-GHz CMOS中功率放大器 3
2.1 功率放大器簡介 3
2.1.1 架構種類與重要參數 4
2.1.2 驅動級線性度之設計考量 7
2.1.3 匹配考量 8
2.1.4 穩定度考量 9
2.2 使用增益提升技巧之94-GHz CMOS中功率放大器 9
2.2.1 電路設計說明與考量 10
2.2.2 設計流程總結 14
2.3 使用增益提升技巧之94-GHz CMOS MPA模擬與量測結果 16
2.3.1 模擬結果 16
2.3.2 量測結果 16
2.4 結果與討論 19
第三章 使用縮小化3-dB正交耦合器之94-GHz CMOS功率放大器 23
3.1 常見之功率結合機制 23
3.1.1 威爾金森功率分波/結合器(Wilkinson power divider/combiner) 23
3.1.2 方向耦合器(Directional coupler) 25
3.1.3 變壓器(Transformer) 25
3.2 使用縮小化3-dB正交耦合器之94-GHz CMOS 功率放大器 27
3.2.1 縮小化3-dB正交耦合器(Miniaturized 3-dB quadrature hybrid) 27
3.2.2 使用縮小化3-dB正交耦合器之94-GHz CMOS功率放大器 30
3.2.3 電路設計說明與考量 31
3.2.4 設計流程總結 35
3.3 使用縮小化3-dB正交耦合器之94-GHz CMOS PA模擬與量測結果 37
3.3.1 模擬結果 37
3.3.2 量測結果 37
3.4 結果與討論 40
第四章 94-GHz CMOS次諧波單混頻器射頻收發機整合晶片 43
4.1 94-GHz CMOS次諧波單混頻器射頻收發機架構簡介 43
4.1.1 射頻收發開關(RF T/R switch) 44
4.1.2 低雜訊放大器(Low-noise amplifier, LNA) 44
4.1.3 可升降頻次諧波混頻器(Up/down conversion sub-harmonic mixer) 44
4.2 應用於94-GHz CMOS次諧波單混頻器射頻收發機之高增益功率放大器 46
4.2.1 電路設計說明與考量 47
4.2.2 設計流程總結 51
4.2.3 模擬結果 53
4.2.4 量測結果 53
4.2.5 結果與討論 56
4.3 94-GHz CMOS次諧波單混頻器射頻收發機整合晶片模擬與量測結果 57
4.3.1 收發機子電路之模擬結果 57
4.3.2 整體收發機之模擬結果 59
4.3.3 整體收發機之量測結果 60
4.4 結果與討論 66
第五章 結論 69
參考文獻 71




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