臺灣博碩士論文加值系統

本論文介紹使用具磁耦合之全通網路架構來實現的數位式相位偏移器。我們分析並利用全通網路中電感間的磁耦合，來提升相位偏移器之頻寬。為驗證設計概念，我們使用TSMC 0.18-µm CMOS製程實現一寬頻四位元相位偏移器。
我們分析全通網路中電感間磁耦合對電路特性的影響。我們利用奇偶模分析推導出具磁耦合的全通網路其S參數，進而得到讓此架構達到全通的頻率響應所需滿足的條件。我們將具磁耦合的全通網路應用於相位偏移器設計，分別分析外接路徑切換開關之對偶網路以及內接切換式電容之單一網路這兩種相移器架構，並求出設計參數與相位偏移量之間的關係。
基於理論分析所得到的結果，我們使用TSMC 0.18-µm CMOS製程設計並實作出一全差動式四位元相位偏移器。電路中的180°相移級使用一對單刀雙擲開關實現，其餘相移級則使用具磁耦合之全通網路來實現，電路架構皆為內接切換式電容之單一網路。其中90°相位級使用串接兩級不同中心頻率的磁耦合全通網路，而45°相移級則使用單級的磁耦合通網路。最後，22.5°相移級則將切換式電容取代為可變電容，用以提供連續的相位偏移；當製程變異過大，可供微調，以得到較準確的相移量。
四位元相移器的量測結果顯示，從1.28 GHz到4.22 GHz，均方根相位誤差均小於3°，相對應的頻寬為106.9%。在頻寬範圍內，返回損耗均大於7.7 dB。植入損耗均小於12.2 dB，振幅誤差皆在±1.5 dB之內。

In this thesis, a digital phase shifter designed based on magnetically coupled all-pass networks (MCAPNs) is presented. The effect of the magnetic coupling between the two inductors within an all-pass network is exploited for increasing the bandwidth of phase shifters. As a proof of concept, a broadband 4-bit phase shifter is implemented in TSMC 0.18-µm CMOS process.
The effect of the magnetic coupling between the two inductors within an all-pass network is analyzed. By even–odd mode analysis, the S parameters of the MCAPN are derived. The conditions for the network to provide an all-pass frequency response are subsequently obtained. Furthermore, the MCAPN is applied to phase shifter design. Two phase-shifter topologies, namely dual networks with external path-select switches and single network with internal switched capacitors, are analyzed. The relations between the design parameters and the phase shift are derived.
Based on the results obtained from the theoretical analysis, a fully-differential 4-bit phase shifter is designed and implemented in TSMC 0.18-µm CMOS process. In the phase shifter, the 180° phase-shifting stage is realized using a pair of single-pole double-throw switches whereas the other phase-shifting stages are constructed using single MCAPN with internal switched capacitors. The 90° phase-shifting stage is constructed by cascading two MCAPNs with different center frequencies whereas the 45° phase-shifting stage consists of only a single MCAPN. Finally, in the 22.5° phase-shifting stage, varactors are used instead of switched capacitors so as to provide a continuous phase shift, which can be fine-tuned in case process variations are too severe.
The measurement results of the 4-bit phase shifter show that the root-mean-square phase error is lower than 3° from 1.28 GHz to 4.22 GHz, corresponding to a 106.9% bandwidth. Within the frequency range, the input and output return losses are greater than 7.7 dB, the insertion loss is less than 12.2 dB, and the amplitude error is within ±1.5 dB for all 16 states.

國 立 中 央 大 學 I
摘要 VI
Abstract VII
目錄 X
圖目錄 XI
表目錄 XII
第一章 緒論 1
1–1　研究動機 1
1–2　文獻回顧 2
1–3　論文架構 4
第二章 理論分析 5
2–1　簡介 5
2–2　全通網路 6
2–3　具磁耦合之全通網路架構分析 9
2-4　相位偏移器之設計分析 13
2–4–1　外接路徑切換開關之對偶網路 14
2–4–2　內接切換式電容之單一網路 17
第三章 使用CMOS製程實現之數位式全通 相位偏移器 20
3–1　簡介 20
3–2　電路設計 21
3–2–1　互相耦合之電感 22
3–2–2　45°與90°數位式相位偏移級 25
3–2–3　180°數位式相位偏移級 30
3–2–4　22.5°類比式相位偏移級 32
3–3　電路模擬及量測結果 35
第四章 結論 41
參考文獻 43

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