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研究生:王俞鈞
研究生(外文):Yu-jin Wang
論文名稱:編織演算法應用於自動化產生ADC實體電容陣列
論文名稱(外文):Weave placement for auto generation physical capacitor array layout on ADC
指導教授:陳竹一
指導教授(外文):Jwu-E Chen
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:31
中文關鍵詞:編織演算法
外文關鍵詞:Weave algorithm
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佈局的自動化設計在類比電路上可以大幅的降低設計時的高錯誤率、高複雜度的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本。由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局,也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等,其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應,以減少一些不匹配的影響。

本論文題出自動化電容排列演算法產生類比/數位轉換器的電容元件,遵守共質心法四項準則,讓陣列中元件可以達到分散、對稱、質心重疊、最密陣列,在以直方圖式的方法來評估模擬INL/DNL,並且將演算法以及評量器整合成一個使用者工具,讓使用者可以直接在陣列上輸入原件就可以快速評估也能手動微調原件位子確保電容比例的準確度

Automated layout design on analog circuits can significantly reduce the high error rate of the design, the time complexity of the layout of the high cost of operation and tedious task and expensive design costs.Due to the mismatch sensitive parasitic capacitance effects, components, process variation and gradient effect will lead to the layout result can be a bad layout, also caused inaccuracies and lower product yield.Most of analog circuits such as analog-digital / digital-to-analog converters or filters, etc., and its performance is dependent on accurate capacitance ratio.For most of the requirements of the exact capacitance ratio of the capacitor in parallel using multiple satellites units substituted single and considering a large parasitic capacitance caused by winding, in order to reduce some of the effects of the mismatch.

This paper propose automatic placement algorithm for analog/digital capacitor device,it follow rule of common-centroid, making the array dispersion, symmetry, coincident
and compactness, we use diagram method to test linearity and integrate algorithm with metric intoa user tool, user can quickly input placement in tool and simulate the result and also do detail change make sure the accurate of capacitor ratio.

摘 要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 vii
Chapter 1. 緒論 .1
1.1動機與背景 .1
1.2論文組織 .2
Chapter 2. 電容陣列區塊佈局概念 .4
2.1電容 .4
2.2電容的不匹配 .7
2.3電容匹配的規則.8
3.1空間相關性.11
Chapter 3. 電容陣列的擺放.15
3.1共質心(Commom-Centroid).15
3.2變異數(Variance)與元件不匹配(Mismatch).17
3.3電容編織排列演算法(Weave).19
3.3.1 SAR ADC電容陣列.19
3.3.2演算法流程.20
Chapter 4 電容陣列INL/DNL數值測量工具(CAMT).22
4.1使用者輸入介面 .22
4.2 CAMT 功用與效能.22
4.3 CAMT使用流程.22
4.3.1 創建矩陣.22
4.3.2矩陣命名及大小設定.23
4.3.3輸入單位電容位子.23
4.3.4結果輸出.24
4.3.5讀取記錄.25
Chapter 5 實驗結果與分析.27
5.1六位元比較.28
Chapter6 結論.29
References.30


References
[1] P.-W. Luo, J.-E. Chen, C.L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu, ”Impact
of capacitance correlation on yield enhancement of mixed-signal/Analog
integrated circuits,” IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 27, No. 11, pp. 2097-2101, November 2008.
[2]D. Sayed and M. Dessouky, “Automatic generation of common-centroid capacitor
arrays with arbitrary capacitor ratio,” in Proc. Des., Automation Test European
Conference, pp. 576–580, Mar. 2002.
[3]P.-W. Luo, J.-E. Chen, M.-Y. Huang, and C.L. Wey, “Design methodology for yield enhancement of switched-capacitor analog integrated circuits,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 1, pp.352-361, Jan. 2011.
[4]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang,” Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, VOL. 31, NO. 12, DECEMBER 2012
[5]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang,”Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” IEEE Design Automation Conference , pp.528-533, 5-9 June 2011
[6]J.-E. Chen, P.-W. Luo, and C.L. Wey, “Yield evaluation of analog placement with
arbitrary capacitor ratio,”Proc. of International Symp. on Quality Electronic
Design, pp. 179-184, 2009.

[8]J.-E. Chen, P.-W. Luo, and C.L. Wey, “Placement optimization for yield Improvement of switched-capacitor analog integrated circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.29, No.2, pp.313318, Feb. 2010.
[15]C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang,“Common-centroid capacitor placement considering systematic and randommismatches in analog integrated circuits,” in Proc. ACM/IEEE Des.Autom. Conf., Jun. 2011, pp. 528–533.
D. Khalil, M. Dessouky, V. Bourguet, M. M. Louerat, A. Catheline, and H. Ragai, “Evaluation of capacitor ratios in automated accurate common centroid capacitor arrays,” in Proc. 6th Int. Symp. Quality Electronics Design, pp. 143–147, Mar. 2005.
Q. Ma, E. F. Y. Young, and K. P. Pun, “Analog placement with common centroid constraints,” Proc.International Conference on Computer-Aided Design, pp. 579-585, 2007.
J. Xiong, V. Zolotov, and H. Lei, “Robust extraction of spatial correlation,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 619–631, Apr. 2007.
D. Johns, and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.
S. Haenzsche, S. Henker and R. Schuffny, “Modeling of capacitor mismatch and non-linearity effects in charge redistribution SAR ADCs,” Proc. Int. Conf. Mixed Design of Integrated Circuits Systems (MIXDEX), pp. 300-305, 2012.

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