由於半導體製程的快速演進，使得晶片上的電晶體尺寸與工作電壓也越來越小，導致電路容易受到雜訊(noise)、傳輸延遲(wire delay)、軟錯誤(soft error)等外在因素影響，而發生時序錯誤(timing error)，其發生原因為資料傳輸時，因受到影響而使電路取樣到錯誤的資料；在邁入先進製程的發展之後，時序錯誤將造成電路運算的可靠度降低。錯誤復原(error-resilient)設計能在電路發生錯誤時立即偵測出錯誤，並且將發生錯誤的資料做修正，使電路回復正常運作的狀態，對於近代的微處理器(microprocessor)而言，已成為不應該缺少的部份。
　　本論文將容忍時序錯誤電路架構應用在與MIPS指令集相容的32位元五級管線微處理器上，以及基於標準元件積體電路設計流程(cell-based IC design flow)來使用Verilog硬體描述語言完成電路的設計，並成功模擬出電路擁有時序錯誤的容忍性；繼而執行邏輯合成(logic synthesis)與靜態時序分析(static timing analysis)的步驟，驗證出時間延遲範圍能符合設定的電路需求後，接著再進行自動化佈局繞線(automatic place and route)與實體驗證(physical verification)，並觀察兩者佈局結果差異。另外在比較與分析數據時，可得知加入容忍時序錯誤設計的電路將能夠改善測試涵蓋率，最後根據實作數據提出結論。

　　Due to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting worse and worse. One of the challenges we are faced with is timing errors of the circuits. Timing errors may happen when transmitted data arrive later than the timing clock or simply has not enough setup time. With VLSI circuit in advanced manufacturing process, timing errors either result in reduced operational reliability of circuits, or we have to tolerate the much slower clock pessimistically. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is even more important for advanced microprocessors in modern technology for many applications in recently years.
　　This master thesis employs timing-error-tolerant circuits in our designed 5-stage pipelined microprocessor with a 32-bit reduced MIPS instruction set. We implement our design using the cell-based IC design flow with Verilog hardware description language. We have run extensive simulation to validate the timing-error-tolerant capability. We then use logic synthesis to generate the circuit, and static timing analysis to verify that the timing delay meets our goal. The final step is to do automatic place and route, physical verification. We measure the cost we have to pay for the timing-error-tolerant capability. It is shown that our design can improve test coverage of the microprocessor with a reasonable cost.

第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 2
1.3 超大型積體電路產生時序錯誤原因之分析 3
1.4 論文組織 4
第二章 相關研究 7
2.1 軟錯誤復原系統 7
2.2 利用C-element電路進行錯誤復原 8
2.3 容忍時序錯誤電路架構 11
2.3.1 Razor架構 11
2.3.2 Razor II架構 13
2.3.3 T-error架構 13
2.4 管線的運作 14
2.5 常見的精簡指令集電腦架構微處理器 15
2.5.1 ARM7微處理器 15
2.5.2 ARM9微處理器 18
2.5.3 MIPS R2000微處理器 20
2.6 優於最差情況設計 21
第三章 容忍時序錯誤電路管線化之設計 23
3.1 設計目標 23
3.2 正反器之使用 23
3.3 電路運作原理 26
3.3.1 利用兩個正反器將錯誤復原 27
3.3.2 利用三個正反器將錯誤復原 28
3.3.3 控制電路設計 29
3.4 管線暫存器內部之正反器電路 35
3.5 容忍時序錯誤電路管線化之問題探討 38
第四章 管線化微處理器之時序錯誤復原 39
4.1 管線化微處理器 39
4.2 管線危障 40
4.2.1 結構危障 41
4.2.2 資料危障 42
4.2.3 控制危障 43
4.3 危障偵測與前饋單元 43
4.4 配合容忍時序錯誤設計所修改之硬體元件 48
4.5 具備容忍時序錯誤功能之微處理器電路 53
4.6 資料路徑 54
第五章 實作與測試 65
5.1 利用電路模擬軟體進行功能模擬 66
5.1.1 原始五級管線微處理器電路模擬結果 71
5.1.2 加入容忍時序錯誤設計之電路模擬結果 74
5.2 電路邏輯合成 78
5.2.1 原始五級管線微處理器電路合成數據 79
5.2.2 加入容忍時序錯誤設計之電路合成數據 81
5.3 靜態時序分析 84
5.3.1 原始五級管線微處理器電路分析情況 84
5.3.2 加入容忍時序錯誤設計之電路分析情況 86
5.4 電路佈局圖 87
5.4.1 原始五級管線微處理器電路佈局圖 88
5.4.2 加入容忍時序錯誤設計之電路佈局圖 89
5.5 電路實體佈局規則驗證 90
5.5.1 對電路實體佈局做DRC驗證 91
5.5.2 對電路實體佈局做LVS驗證 92
5.6 實作與測試數據比較 93
第六章 結論 103
參考文獻 105

[1] H. Asadi and M.B. Tahoori, "Soft Error Hardening for Logic-Level Designs," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 4139-4142, May 2006.
[2] Y. Huang, W.T. Cheng, S.M. Reddy, C.J. Hsieh, and Y.T. Hung, "Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault," Proceedings of IEEE International Test Conference, pp. 319-328, September 2003.
[3] E.V. Vijay, C.V.R. Rao, E.V. Kumar, and G.N. Swamy, "Electronic Control Unit for an Adaptive Cruise Control System & Engine Management System in a Vehicle using Electronic Fuel Injection," Proceedings of International Conference on Emerging Trends in Robotics and Communication Technologies, pp. 143-146, December 2010.
[4] Y.Y. Chen and C.M. Lyu, "ECU-level Fault-Tolerant Framework for Safety-Critical FlexRay Network Systems," Proceedings of International Conference on ICT Convergence, pp. 533-558, October 2012.
[5] R. Guo and S. Venkataraman, "A Technique for Fault Diagnosis of Defects in Scan Chains," Proceedings of IEEE International Test Conference, pp. 268-277, November 2001.
[6] J.C.M. Li, "Diagnosis of Single Stuck-at Faults and Multiple Timing Faults in Scan Chains," Journals of IEEE Transactions on VLSI Systems, Vol. 13, No. 6, pp. 708-718, June 2005.
[7] T. Austin, V. Bertacco, D. Blaauw, and T. Mudge, “Opportunities and Challenges for Better than Worst-Case Design,” Proceedings of Asia-South Pacific Design Automation Conference, January 2005.
[8] S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia, and K.S. Kim, "Logic Soft Errors: A Major Barrier to Robust Platform Design," Proceedings of IEEE International Test Conference, pp. 1-10, November 2005.
[9] S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas, and K.S. Kim, "Combinational Logic Soft Error Correction," Proceedings of IEEE International Test Conference, pp. 1-9, October 2006.
[10] S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, "Soft Error Resilient System Design through Error Correction," Proceedings of IFIP International Conference on VLSI, pp. 332-337, October 2006.
[11] M. Zhang, T.M. Mak, J. Tschanz, K.S. Kim, N. Seifert, and D. Lu, "Design for Resilience to Soft Errors and Variations," Proceedings of 13th IEEE International On-line Testing Symposium, pp. 23-28, July 2007.
[12] S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas, and K.S. Kim, "Built-In Soft Error Resilience for Robust System Design," Proceedings of IEEE International Conference on Integrated Circuit Design and Technology, pp. 1-6, September 2007.
[13] D. Ernst, S. Pant, R. Rao, C. Ziesler, D. Blaauw, T. Austin, K. Floutner, and T. Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture, pp. 7-18, 2003.
[14] T. Austin, D. Blaauw, T. Mudge, and K. Flautner, "Making Typical Silicon Matter with Razor," Journals of IEEE Transactions on Computer Society, Vol. 37, No. 3, pp. 57-65, 2004.
[15] D. Blaauw, S. Kalaiselvan, K. Lai, W.H. Ma, S. Pant, C. Tokunaga, S. Das, and D. Bull, "Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance," Proceedings of IEEE International Solid-State Circuits Conference, pp. 400-622, February 2008.
[16] S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, "Timing Error Tolerance in Nanometer ICs," Proceedings of IEEE 16th International On-Line Testing Symposium, pp. 283-288, July 2010.
[17] S. Valadimas, Y. Tsiatouhas, A. Arapoyanni, and A. Evans, "Single Event Upset Tolerance in Flip-Flop Based Microprocessor Cores," Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 79-84, October 2012.
[18] A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, "Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability," Proceedings of Asia and South Pacific Conference on Design Automation, pp. 24-27, January 2006.
[19] S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, and K. Flautner, "A Self-Tuning DVS Processor using Delay-Error Detection and Correction," Proceedings of Symposium on VLSI Circuits, pp. 258-261, June 2005.
[20] J. Geun-Young, P. Ju-Sung, J. Hyun-Woo, Y. Byung-Woo, and L. Myung-Jin, "ARM7 Compatible 32-bit RISC Processor Design and Verification," Proceedings of the 9th Russian-Korean International Symposium on Science and Technology, pp. 304-312, October 2009.
[21] C.C. Arandilla, J.B.A. Constantino, A.O.M. Glova, A.P. Ballesil-Alvarez, and J.A.P. Reye, "High-level Implementation of the 5-Stage Pipelined ARM9TDM Core," Proceedings of IEEE Region 10 Conference, pp. 1696-1700, November 2010.
[22] R. Tamhankar, S. Murali, S. Stergiou, A. Pullini, F. Angiolini, L. Benini, and G. De Micheli, "Timing-Error-Tolerant Network-on-Chip Design Methodology," Journals of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 7, pp. 1297-1310, July 2007.
[23] R.R. Tamhankar, S. Murali, and G. De Micheli, "Performance Driven Reliable Link Design for Networks on Chips," Proceedings of Asia and South Pacific Design Automation Conference, Vol. 2, pp. 749-754, January 2005.
[24] S. Murali, R. Tamhankar, F. Angiolini, A. Pulling, D. Atienza, L. Benini, and G.D. Micheli, "Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips," Proceedings of International Symposium on System-on-Chip, pp. 1-4, November 2006.
[25] A. Floros, Y. Tsiatouhas, A. Arapoyanni, and T. Haniotakis, "A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism," Proceedings of 13th IEEE International Conference on Electronics Circuits and Systems, pp. 692-695, December 2006.
[26] S.M. Reddy, I. Pomeranz, S. Kajihara, A. Murakami, S. Takeoka, and M. Ohta, "On Validating Data Hold Times for Flip-Flops in Sequential Circuits," Proceedings of IEEE International Test Conference, pp. 317-325, October 2000.
[27] M. Zhang, S. Mitra, T.M. Mak, N. Seifert, N.J. Wang, Q. Shi, K.S. Kim, N.R. Shanbhag, and S.J. Patel, "Sequential Element Design with Built-In Soft Error Resilience," Journals of IEEE Transactions on VLSI Systems, Vol. 14, No. 12, pp. 1368-1378, December 2006.
[28] Y. Lin and M. Zwolinski, "SETTOFF: A Fault Tolerant Flip-Flop for Building Cost-efficient Reliable Systems," Proceedings of IEEE 18th International On-Line Testing Symposium, pp. 7-12, 2012.
[29] N. Pinckney, T. Barr, M. Dayringer, M. McKnett, N. Jiang, C. Nygaard, D.M. Harris, J. Stanley, and B. Phillips, "A MIPS R2000 Implementation," Proceedings of ACM/IEEE Design Automation Conference, pp. 102-107, June 2008.
[30] D. Bull, S. Das, K. Shivashankar, G.S. Dasika, K. Flautner, and D. Blaauw, "A Power-Efficient 32-bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation," Journals of IEEE Solid-State Circuits, Vol. 46, No. 1, pp. 18-31, January 2011.
[31] M.N. Topiwala and N. Saraswathi, "Implementation of a 32-bit MIPS Based RISC Processor using Cadence," Proceedings of International Conference on Advanced Communication Control and Computing Technologies, pp. 979-983, May 2014.
[32] S.Z. Shazli and M.B. Tahoori, "Transient Error Detection and Recovery in Processor Pipelines," Proceedings of 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 304-312, October 2009.
[33] CIC Design Service Department, "CIC Referenced Flow for Cell-Based IC Design," Version 1.0, National Chip Implementation Center, Hsinchu, 2008.
[34] C.M. Huang, "Cell-Based IC Design Concepts," Training Manual, National Chip Implementation Center, Hsinchu, 2013.
[35] H.L. Chen, "Verilog," Training Manual, National Chip Implementation Center, Hsinchu, 2015.
[36] S.S. Wang, "Logic Synthesis with Design Compiler," Training Manual, National Chip Implementation Center, Hsinchu, 2015.
[37] C.L. Huang, "Timing and Power Sign-Off with PrimeTime," Training Manual, National Chip Implementation Center, Hsinchu, 2011.
[38] L.Y. Lin, "Cell-Based IC Physical Design and Verification with IC Compiler," Training Manual, National Chip Implementation Center, Hsinchu, 2015.
[39] C.B. Lin, "Physical Verification with Calibre," Training Manual, National Chip Implementation Center, Hsinchu, 2015.
[40] David A. Patterson and John L. Hennessy, "Computer Organization and Design: The Hardware/Software Interface," 3rd Edition, Morgan Kaufmann Publishers, 2004.
[41] John L. Hennessy and David A. Patterson, "Computer Architecture: A Quantitative Approach," 4th Edition, Morgan Kaufmann Publishers, 2006.
[42] S. Furber, "ARM System-on-Chip Architecture," 2nd Edition, Addison Wesley, pp. 248-262, 2000.
[43] E. Brunvand, "Digital VLSI Chip Design with Cadence and Synopsys CAD Tools," Addison Wesley, 2009.
[44] S. Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis," 2nd Edition, Prentice Hall, 2003.
[45] M. Morris Mano and Michael D. Ciletti, "Digital Design," 4th Edition, Prentice Hall, 2006.
[46] Neil H. E. Weste and David Harris, "CMOS VLSI Design: A Circuit and Systems Perspective," 3rd Edition, Addison Wesley, 2006.
[47] Keshab K. Parhi, "VLSI Digital Signal Processing Systems: Design and Implementation," John Wiley & Sons, 1999.
[48] K. Martin, "Digital Integrated Circuit Design," Oxford University Press, pp. 284-321, 2000.
[49] G. Kane, "MIPS R2000 RISC Architecture," Prentice Hall, 1987.
[50] R. Britton, "MIPS Assembly Language Programming," Prentice Hall, 2003.