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研究生:彭冠霖
研究生(外文):Guan-Lin Peng
論文名稱:容忍時序錯誤微處理器之超大型積體電路設計
論文名稱(外文):VLSI Design of a Timing-Error-Tolerant Microprocessor
指導教授:紀新洲
指導教授(外文):Hsin-Chou Chi
學位類別:碩士
校院名稱:國立東華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
論文頁數:108
中文關鍵詞:錯誤容忍錯誤復原微處理器超大型積體電路設計
外文關鍵詞:fault toleranceerror resiliencemicroprocessorVLSI design
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  由於半導體製程的快速演進,使得晶片上的電晶體尺寸與工作電壓也越來越小,導致電路容易受到雜訊(noise)、傳輸延遲(wire delay)、軟錯誤(soft error)等外在因素影響,而發生時序錯誤(timing error),其發生原因為資料傳輸時,因受到影響而使電路取樣到錯誤的資料;在邁入先進製程的發展之後,時序錯誤將造成電路運算的可靠度降低。錯誤復原(error-resilient)設計能在電路發生錯誤時立即偵測出錯誤,並且將發生錯誤的資料做修正,使電路回復正常運作的狀態,對於近代的微處理器(microprocessor)而言,已成為不應該缺少的部份。
  本論文將容忍時序錯誤電路架構應用在與MIPS指令集相容的32位元五級管線微處理器上,以及基於標準元件積體電路設計流程(cell-based IC design flow)來使用Verilog硬體描述語言完成電路的設計,並成功模擬出電路擁有時序錯誤的容忍性;繼而執行邏輯合成(logic synthesis)與靜態時序分析(static timing analysis)的步驟,驗證出時間延遲範圍能符合設定的電路需求後,接著再進行自動化佈局繞線(automatic place and route)與實體驗證(physical verification),並觀察兩者佈局結果差異。另外在比較與分析數據時,可得知加入容忍時序錯誤設計的電路將能夠改善測試涵蓋率,最後根據實作數據提出結論。
  Due to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting worse and worse. One of the challenges we are faced with is timing errors of the circuits. Timing errors may happen when transmitted data arrive later than the timing clock or simply has not enough setup time. With VLSI circuit in advanced manufacturing process, timing errors either result in reduced operational reliability of circuits, or we have to tolerate the much slower clock pessimistically. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is even more important for advanced microprocessors in modern technology for many applications in recently years.
  This master thesis employs timing-error-tolerant circuits in our designed 5-stage pipelined microprocessor with a 32-bit reduced MIPS instruction set. We implement our design using the cell-based IC design flow with Verilog hardware description language. We have run extensive simulation to validate the timing-error-tolerant capability. We then use logic synthesis to generate the circuit, and static timing analysis to verify that the timing delay meets our goal. The final step is to do automatic place and route, physical verification. We measure the cost we have to pay for the timing-error-tolerant capability. It is shown that our design can improve test coverage of the microprocessor with a reasonable cost.
第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 2
1.3 超大型積體電路產生時序錯誤原因之分析 3
1.4 論文組織 4
第二章 相關研究 7
2.1 軟錯誤復原系統 7
2.2 利用C-element電路進行錯誤復原 8
2.3 容忍時序錯誤電路架構 11
2.3.1 Razor架構 11
2.3.2 Razor II架構 13
2.3.3 T-error架構 13
2.4 管線的運作 14
2.5 常見的精簡指令集電腦架構微處理器 15
2.5.1 ARM7微處理器 15
2.5.2 ARM9微處理器 18
2.5.3 MIPS R2000微處理器 20
2.6 優於最差情況設計 21
第三章 容忍時序錯誤電路管線化之設計 23
3.1 設計目標 23
3.2 正反器之使用 23
3.3 電路運作原理 26
3.3.1 利用兩個正反器將錯誤復原 27
3.3.2 利用三個正反器將錯誤復原 28
3.3.3 控制電路設計 29
3.4 管線暫存器內部之正反器電路 35
3.5 容忍時序錯誤電路管線化之問題探討 38
第四章 管線化微處理器之時序錯誤復原 39
4.1 管線化微處理器 39
4.2 管線危障 40
4.2.1 結構危障 41
4.2.2 資料危障 42
4.2.3 控制危障 43
4.3 危障偵測與前饋單元 43
4.4 配合容忍時序錯誤設計所修改之硬體元件 48
4.5 具備容忍時序錯誤功能之微處理器電路 53
4.6 資料路徑 54
第五章 實作與測試 65
5.1 利用電路模擬軟體進行功能模擬 66
5.1.1 原始五級管線微處理器電路模擬結果 71
5.1.2 加入容忍時序錯誤設計之電路模擬結果 74
5.2 電路邏輯合成 78
5.2.1 原始五級管線微處理器電路合成數據 79
5.2.2 加入容忍時序錯誤設計之電路合成數據 81
5.3 靜態時序分析 84
5.3.1 原始五級管線微處理器電路分析情況 84
5.3.2 加入容忍時序錯誤設計之電路分析情況 86
5.4 電路佈局圖 87
5.4.1 原始五級管線微處理器電路佈局圖 88
5.4.2 加入容忍時序錯誤設計之電路佈局圖 89
5.5 電路實體佈局規則驗證 90
5.5.1 對電路實體佈局做DRC驗證 91
5.5.2 對電路實體佈局做LVS驗證 92
5.6 實作與測試數據比較 93
第六章 結論 103
參考文獻 105
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