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研究生:劉秉竑
研究生(外文):Ping-Hung Liu
論文名稱:具二進制權重機制之CMOS數位至時間轉換器
論文名稱(外文):具二進制權重機制之CMOS數位至時間轉換器
指導教授:陳俊吉陳俊吉引用關係
指導教授(外文):Chun-Chi Chen
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:48
中文關鍵詞:數位至時間轉換器脈衝擴增二進制權重互補式金氧半
外文關鍵詞:CMOSDigital-to-Time ConverterPulseBinary weighted
相關次數:
  • 被引用被引用:2
  • 點閱點閱:153
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文提出具二進制權重機制的數位至時間轉換器(DTC),以脈衝混合機制為基礎來實現其脈衝擴增,所提電路架構以脈衝產生電路(Pulse Generator, PG)、脈衝擴增電路(Pulse-Expanding Circuit, PEC)以及時間扣抵電路(Time Substractor, TS)所組成;脈衝擴增電路為此電路核心,可根據輸入數值(n)來擴增相對應之時間寬度,亦即數位至時間轉換,無須相對延遲線架構或高位元DAC即可有良好的解析度,是以大大地降低電路複雜度而可用較低之成本來實現;脈衝擴增區塊由一個2對1多工器(MUX)與一個脈衝擴增單元(Pulse-Expanding Unit,PEU)來組成,N位元脈衝擴增電路即須N個2對1 MUX與N個脈衝擴增單元(PEU)來實現,再則,本電路運用脈衝中和原理,抵補電路架構中因非均質元件而造成額外之縮減或擴增量(脈衝改變量),如此可使電路中脈衝改變量全由脈衝擴增電路所控制以提升精確度。脈衝產生電路的作用為先產生一額外脈衝以輸入脈衝擴增電路作脈衝擴增功能,最後再利用時間扣抵電路扣除先前所產生之脈衝寬度,所以整體電路之時間產生可只與數位輸入值(n)有關。本論文實作之全數位四位元CMOS數位至時間轉換器以TSMC 0.35-µm製程製作,晶片面積只有0.02mm2,其解析度為5微微秒(ps),本論文之數位至時間轉換器不僅成本低且達成不錯的解析度。
An all-digital CMOS digital-to-time converter (DTC) based on binary-weighted scheme is presented in this dissertation. The pulse expansion is fulfilled by pulse-mixing scheme to perform digital-to-time conversion. A concise structure can be realized without requiring Vernier principle or high-bit DACs to save circuit cost. First, a pulse generator (PG) is added to generate an additional time offset for pulse expansion. Then, a pulse-expanding circuit (PEC) with a binary-weighted scheme, implemented by pulse-expanding units (PEUs) and simple 2-to-1 MUXs, is proposed to generate a programmable time generation. After the PEC, the identical time offset can be eliminated by a time subtractor (TS). Moreover, a pulse neutralization technique is presented to eliminate the undesired varied amount for accuracy improvement. The all-digital 4-bit CMOS converter was implemented in 0.35-µm TSMC CMOS process and occupied 0.02 mm2 only. The resolution is measured as 5 ps. The proposed DTC not only has a favorable circuit cost but also achieves an acceptable resolution.
中文摘要 I
ABSTRACT II
誌謝 III
目錄 IV
表目錄 V
圖目錄 VI
一、緒論 - 1 -
1.1 研究動機 - 1 -
1.2 論文架構 - 4 -
二、數位至時間轉換器之介紹 - 5 -
2.1 簡介 - 5 -
2.3 相對時間延遲數位至時間轉換器 - 7 -
三. 具二進制權重機制之CMOS數位至時間轉換器 - 12 -
3.1 整體電路架構 - 12 -
3.2 脈衝改變機制 - 14 -
3.2.1 以反閘實現單端脈衝縮減單元 - 14 -
3.2.2 以反閘實現單端脈衝擴增單元 - 18 -
3.2.3 以反閘實現雙端脈衝混合單元[35] - 20 -
3.3電路區塊介紹 - 22 -
3.3.1 脈衝擴增電路(PEC) - 22 -
3.3.2 電容式脈衝縮減單元 - 23 -
3.3.3 電容式脈衝擴增單元 - 25 -
3.3.4 電容式脈衝改變電路與相對延遲時間延遲線比較 - 26 -
3.3.5 本電路實現之電容式雙端脈衝混合單元 - 28 -
3.3.6 脈衝中和機制 (Pulse Nebulization Scheme) - 30 -
3.3.7 脈衝產生器(Pulse Generator, PG) - 34 -
3.3.8 時間扣抵電路(Time Substractor) - 36 -
四、電路設計與模擬 - 37 -
4.1 電路架構 - 37 -
4.2 脈衝產生器死亡時間(dead time or offset error)模擬驗證 - 37 -
4.3 整體電路模擬驗證 - 38 -
五、結論 - 45 -
5.1 結論 - 45 -
參考文獻 - 46 -
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