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研究生:李宏騏
研究生(外文):Hong-Chi Li
論文名稱:可重組多重BCH碼率產生器之研究
論文名稱(外文):可重組多重BCH碼率產生器之研究
指導教授:洪金車
指導教授(外文):King-Chu Hung
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:105
中文關鍵詞:BCH碼線性回歸移位暫存器
外文關鍵詞:LFSRBCH Code
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固態硬碟(SSD)是目前市場上最被廣泛運用的儲存裝置,然而,固態硬碟的高速讀/寫以及可靠性提升到現今都是一項重要的研究議題,許多錯誤糾正碼(ECC)嵌入在快閃記憶體內,解決上述問題。
BCH碼具有優秀的糾錯能力,與較低硬體複雜度,被廣泛運用於ECC的設計中。在本論文中我們提出一個可重組多重BCH碼率產生器之研究,直接輸入訊號而不再經過額外的生成多項式計算即可得到結果。
與最新的技術相比,所提出的BCH編碼設計殼可以節省邏輯閘的使用和最小的關鍵路徑延遲是使用Synopsys(Verilog、Verdi、Design Compiler、Synthesis、PrimeTime®) 和 Cell Library(TSMC 90nm CLN90G)實現。
Solid-state disks (SSD) are widely used storage devices in current consumer electronics. However, the enhancement of SSD data retention and reliability given the high read/write activity are critical research topics. Many error correction codes (ECC) have been developed in the literature to solve the aforementioned issues by embedding ECC design in flash memory.
Bose–Chaudhuri–Hocquenghen (BCH) code is the most widely adopted ECC design owing to its error-correcting capability and hardware complexity. In this paper, we propose A Study of Configurable Multiple BCH Coderate Generator that directly codes the input message without extra operations in the generation polynomial term.
Compared with state-of-the-art designs, the proposed BCH coding design can save logic gate use and minimize the critical path delay with Synopsys(Verilog、Verdi、Design Compiler、Synthesis、PrimeTime®) and Cell Library(TSMC 90nm CLN90G).
中文摘要…………………………………………………………………………………I
英文摘要………………………………………………………………………………...II
誌謝…………………………………………………………………………………….III
目錄…………………………………………………………………………………….IV
圖目錄………………………………………………………………………………….VI
表目錄………...………………………………………………………………………..IX
第一章 緒論 1
1.1 研究動機 1
1.2 錯誤更正碼簡介 4
1.3 論文架構 6
第二章 抽象代數與BCH碼的基礎與應用 7
2.1 群(Group) 7
2.2 環(Ring) 8
2.3 場(Field) 8
2.4 BCH碼基本定義 15
2.5 BCH編碼流程 19
第三章 傳統序列與平行方式BCH編碼硬體架構 22
3.1 序列方式BCH編碼器 22
3.2 平行方式BCH編碼器 49
第四章 可重組多重BCH碼率產生器之研究 54
4.1 可重組多重BCH碼率展開式序列編碼 54
4.2 可重組多重BCH碼率軟體實現與建立查表 58
4.3 可重組多重BCH碼率硬體架構實現 64
第五章 實驗結果 79
5.1 傳統BCH序列方式編碼 79
5.2 狀態機BCH序列方式編碼 81
5.3 可重組多重BCH碼率產生器 83
第六章 結論 87
6.1 結論 87
6.2 未來展望 87
參考文獻 91
[1]Y. M. Lin, C. H. Yang, C. H. Hsu, H. C. Chang, and C. Y. Lee, “A MPCN-based parallel architecture in BCH decoders for NAND flash memories,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 58, no. 10, pp. 682-686, Oct. 2011.
[2]H. Kim et al., “A 159 mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper (ISSCC), Feb. 2010, pp. 442-443.
[3]Y. Li et al., “128 Gb 3b/cell NAND flash memory in 19nm technology with 18 MB/s write rate and 400 Mb/s toggle mode,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper (ISSCC), Feb. 2012, pp. 436-437.
[4]G. Fettweis and M. Hassner, “A combined Reed-Solomon encoder and syndrome generator with small hardware complexity,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 4. May 1992, pp. 1871-1874.
[5]C. L. Lin, C. L. Chen, H. C. Chang, and C. Y. Lee, “Jointly designed nonbinary LDPC convolutional codes and memory-based decoder architecture,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 62, no. 10, pp. 2523-2532, Oct. 2015.
[6]S. Li and T. Zhang, “Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding,”IEEE Trans.VLSI syst., vol.18,no. 10,pp.1412-1420,Oct.2010.
[7]K. K. Parhi,“Eliminating the fanout bottleneck in parallel long BCH encoders,” IEEE Trans. Circuits Syst. I:Reg. Papers, vol. 51, no. 3, pp. 512-516, Mar. 2004.
[8]X. Zhang, and K. K. Parhi, “High-speed architectures for parallel long BCH encoders,”IEEE Trans.VLSI syst., vol.13,no. 7,pp.872-877,Jul. 2005.
[9]W. Liu, J. Rho, and W. Sung, “Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories,” in IEEE Workshop on Signal Processing Systems Design and Implementation, 2006, pp. 303-308.
[10]H. Chen, “CRT-based high-speed parallel architecture for long BCH encoding,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 56, no. 8, pp. 684-686, Aug. 2009.
[11]Y. Lee, H. Yoo, I. Yoo, and I. C. Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” in Proc. IEEE. Int. Solid-State Circuits Conf. (ISSCC), 2012, pp. 426-428.
[12]H. Yoo, J. Jung, J. Jo, and I. C. Park, “Area-Efficient multimode encoding architecture for long BCH codes,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 60, no. 12, pp. 872-876, Dec. 2013.
[13]H. Yoo, Y. Lee, and I. C. Park, “7.3 Gb/s universal BCH encoder and decoder for SSD controllers,” in Proc. IEEE. Int. Design Automation Conf., 2014, pp.37-38.
[14]C. H. Yang,Y. M. Lin, H. C. Chang, and C. Y. Lee,“An MPCN-based BCH codec architecture with arbitrary error correcting capability,”IEEE Trans. VLSI syst., vol.23, no. 7, pp. 1235-1244, Jul. 2015.
[15]Y. M. Lin, H. C. Chang, and C. Y. Lee, “Improved high code-rate software BCH decoder architectures with one extra error compensation,” IEEE Trans. VLSI syst., vol. 21, no. 11, pp. 2160-2164, Nov. 2013.
[16]J. Cho and W. Sung, “Efficient software-based encoding and decoding of BCH codes,” IEEE Trans. Comput., vol. 58, no. 7, pp. 878-889, Jul. 2009.
[17]R. Cherukuri, “Agile encoder architecture for strength-adaptive long BCH codes,”in Proc. IEEE GLOBECOM, Dec. 2010, pp. 1900–1904.
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