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研究生:陳俊佑
研究生(外文):Chun-Yu Chen
論文名稱:奈米線電晶體在矽覆絕緣之分析與模型
論文名稱(外文):Analysis and Modeling of Nanowire MOSFETs on SOI Substrate
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:博士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:英文
論文頁數:182
中文關鍵詞:製作技術離散摻雜影響三維數值模擬鰭式場效應電晶體無接式場效應電晶體鍺與III-V整合精簡模型奈米線設計窗
外文關鍵詞:JunctionlessCompact ModelBulk FinFETsemiconductor technology technique for manufacturingTCAD SimulationRandom Dopant FluctuationIII-V and GeNanowireDesign Window
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場效應電晶體從1947年被發明至今,走過無數的蛻變,從單純的尺寸微縮,由光學步進曝光機到電子束微影系統微縮至20奈米。從高K值氧化層選擇與金屬閘極選擇,汲源極矽鍺應力增強。氧化層上矽的使用,衝擊離子化特性使邏輯運算速度增快,然而,場效應電晶體即將走入多閘極鰭式電晶體量產,傳統場效應電晶體與多閘極之間是否存在共通的設計?是本論文所研究的主軸。
本論文主要從場效應電晶體的設計窗之研究,考量各種參數對於奈米線電晶體的影響,從傳統場效應電晶體的設計窗為出發點,延伸至與最具微縮性的奈米線場效應電體研究,透過學理分析與三維數值模擬,深入探討奈米線電晶體微縮能力,以及對抗短通道效應的能力。此外,我們也對於環繞式閘極的電容特性,做一精簡模型,與傳統的平面式計算的差別,最後與TCAD相互驗證。
而製程技術不斷的持續進步,在極度微縮的過程中,摻雜在電晶體中的難度也隨著急速上升,在傳統電晶體中離散摻雜影響十分嚴重,本文也對於離散摻雜效應在多閘極電晶體下特性比較,根據傳統的設計,使其離散分佈在通道中,使用統計方式比較其特性走向;而無接式場效應電晶體的發明,使摻雜困難度減低,也是本文討論的目標。離散原子是否也如傳統電晶體設計般,有嚴重的臨界電壓差異?或者有其他主要影響臨界電壓的因子存在?本論文採用高斯分佈來設計離散原子在無接面式電晶體中的影響,並同時討論氧化層厚度、矽薄膜厚度、金屬工函數影響與閘極致汲源延伸區,歸納出製程上影響臨界電壓最劇烈的參數。
而在製作技術上,鰭式場效應電晶體的製作已成為主流,在製程中可以微縮與應用的參數,本論文也將其討論相關製作方式,最後與先前的推論做驗證。然而,如何超越摩爾定律?在本論文中也提供兩種設計方式,其中一種是衝擊離子化在多閘極場效應電晶體,以具有微縮代表性的奈米線為範例,其次為非矽半導體整合,以鍺與III-V整合在同一基板為出發,延伸鰭式場效應電晶體的技術,在主要不同的主動區為探討製作上的差異。
The MOSFET transistor devices have been invented since 1947. From I-Line dimension to E-beam writer, MOSFETs have gone through a series of revolution in semiconductor industry such as high-k dielectrics oxide and metal gate. The source/drain material is now implemented with SiGe for strain purpose. SOI technology has been used in logic design, unique impact ionization of which can be beneficial to performance. Among multiple-gate devices, FinFET is emerging for manufacturing. How to account for the new physics of multiple gate devices in logic design is addressed in this thesis. Furthermore, the thesis also presents some issues and solutions when applying for the conventional design window to the multiple gate devices.
This thesis reviews the design window of MOSFET devices based on conventional bulk transistors, which can be extended to nanowire transistor design. A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22 nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this thesis shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension.
When the devices technology continues to scale, the doping engineering is becoming more difficult. This thesis presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes the predominant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when the ratio of film thickness to channel length is less than one quarter, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.
As end of technology roadmap is being approached, many solutions to extend Moore’s Law have been proposed. When the device dimension continues to shrink, and the leakage current, mainly coming from the short-channel effects, becomes a limiting factor, the supply bias, i.e. VDD, has to decrease accordingly. However, in order to provide a good CMOS logic function, the transistor on-off current ratio, which is linked to subthreshold swing, has to stay above at least four orders. Such limitation has prevented the supply bias from further reduction. For low power application, the off leakage current is strictly limited. To gain better performance at same leakage, we will need to lower swing. The subthreshold kink effect enables the use of low supply bias without compromising performance for gate-all-around MOSFETs. This thesis is organized as follows; Chapter 1 introduces the semiconductor technology technique for manufacturing bulk FinFETs. Chapter 2 presents nanowire device scaling and design window. Chapter 3 presents a study of junctionless MOSFETs with a focus on random doping fluctuation effect. Chapter 4 presents beyond Moore’s law including the super steep subthreshold swing design and Chapter 5 presents future work on the silicon integration of Ge and III-V.
摘要 i
Abstract iii
CONTENTS vi
Figure Caption ix
Table Caption xix
Chapter 1 Introduction 1
1 - 1. MOSFET Evolution 1
1 - 2. Device scaling and Motivation 3
1 - 3. Bulk FinFET Manufacture and calibration 4
1 - 4. Bulk FinFET Experiment Results and Discussion 13
1 - 5. Summary 24
Chapter 2 Nano Device Scaling and Design Window 25
2 - 1. Design Introduction 26
2 - 2. Scaling insight and performance projection 28
2 - 3. Analysis for design considerations 37
2 - 3 - 1. Design consideration for bulk mosfets 37
2 - 3 - 2. Design consideration for nanowire mosfets 39
2 - 4. Evaluation of nanowire diameter 42
2 - 5. Summary 47
Chapter 3 Random Doping Fluctuation and Junctionless Study 48
3 - 1. Simulation Techniques for Nanowire Transistors 50
3 - 1 - 1. Results and Discussion 52
3 - 1 - 2. Discrete Dopant Fluctuation along the Channel 54
3 - 1 - 3. Discrete Dopant Fluctuation across the Wire 56
3 - 1 - 4. Variability in Silicon Nanowire MOSFETs 59
3 - 1 - 5. Summary 60
3 - 2. Junctionless Nanowire FET on SOI Substrate 61
3 - 2 - 1. Design Introduction 61
3 - 2 - 2. Simulation methodology 62
3 - 2 - 3. Performance Comparison 64
3 - 2 - 4. Summary 72
3 - 3. Threshold Voltage Variability Analysis and Design Insights for Junctionless Double-Gate Transistors 73
3 - 3 - 1. Design Introduction 73
3 - 3 - 2. Random Discrete Doping for Double- Gate Transistors 75
3 - 3 - 3. Comprehensive analysis to account for additional fluctuations 78
3 - 3 - 4. Summary 90
Chapter 4 More Moore’s Law 91
4 - 1. Design Introduction 93
4 - 2. Simulation methodology 96
4 - 3. Nanowire Device Design and performance projection 98
4 - 4. Analysis and Modeling for subthreshold kink 105
4 - 4 - 1. Evaluation of subthreshold kink for SOI nanowire MOSFETs 105
4 - 4 - 2. Impact of VDS and voltage scalability 113
4 - 4 - 3. Analytical modeling of subthreshold kink for SOI nanowire MOSFETs 114
4 - 5. Summary 120
Chapter 5 Conclusion 121
Summary this thesis 121
5 - 1. Future Work 122
5 - 1 - 1. Structure Design with Fins 123
Reference 127
Appendix - A 141
Appendix - B 152
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