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研究生:曾偉岳
研究生(外文):Tseng, Weu-Yuen
論文名稱:3D IC封裝高性能多重來料Pick & Place建構發展決策模型及其實證研究
論文名稱(外文):3D IC bumping high performance Multi-source Pick & Place Equipment Development
指導教授:簡禎富簡禎富引用關係
指導教授(外文):Chien, Chen-Fu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:經營管理碩士在職專班
學門:商業及管理學門
學類:企業管理學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:英文
論文頁數:19
中文關鍵詞:CoWoS 3D IC 封裝技術New tool purchase spec決策分析Pick and place WPH改善
外文關鍵詞:CoWoS 3D IC packageNew tool Purchase spec decision makingPick and place WPH improvement
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CoWoS (Chip-on-Wafer-on-Substrate ) :,採用矽穿孔(through-silicon vias, TSVs)的矽晶圓當作載具,在單一元件中整合數枚晶片以減低功耗、改善系統特性以及縮小物件尺寸。先以CoW技術將矽晶片連接到經過TSV處理的晶圓後,再將這個次系統附著到基板上以組成最後的元件(oS) 。
CoWoS晶片必須透過Pick and Place (PnP) 將不同 Chip整合到Substrate 上,是最關鍵的技術,也是Bottleneck 。改善
本論文即為探論建構新產能時,機台的purchase spec決策分析。

With the absent of the end of Moore’s Law, all semiconductor foundries are working on another way to break through the physics limitation. All this efforts such as MEMS, Ultra-Low-Power IC, Mixed Signal IC and 3D-IC etc are called “More-than-Moore.” Among More-than-Moore, the most likely solution to extend Moore’s Law is the 3D-IC technology. As a core process of 3D-IC, Pick & Place process (P&P) is getting more and more important and being expected to have more powerful function nowadays. Traditionally in prior art, tool only allows 10 configurations to select and re-arrange
different bin codes, but the customer usually have more than 10 configurations on each order. As a result of that, manually revising bin configurations during an order is needed. That causes the automation of equipment to be limited. Another issue is for the next generation 3D-IC based GPU, DRAM and GPU have to do P&P in the same stage in order to cost down. DRAM likely comes from Tape & Reel (T&R) or Film Frame (FF) packages, and GPU comes from film frame package (but with 2 different types.) The above complexity causes P&P process manually, low WPH, high MO risk and high CoO. We developed an all in one die bonder as a solution, it merges T&R, 2 types of film frame process in the same time and it’s automatically, high WPH, no MO risk and lower CoO. Moreover, it supports bin configurations to be controlled by each substrate to solve the 10 configuration limitation and to achieve the real automation.

1.Introduction/ Purpose..... 1
2.Literature survey......... 6
3.Study Architecture........ 8
4.Empirical Study........... 11
5.Conclusion................ 17
Reference................... 18

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簡禎富、陳勁甫、林國義(2013),在新竹科學工業園區及週邊規劃研究園區之研究,管理與系統,20卷2期,頁227-255。
簡禎富、游智閔、徐紹鐘(2009),紫式決策分析以建構半導體晶圓廠人力規劃決策模型,管理與系統,16卷2期,頁157-180。
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簡禎富、施義成、林振銘、陳瑞坤(2005),半導體製造技術與管理,清華大學出版社,新竹。
Chien, C. -F., Wang, H. -J., & Wang, M. (2007), "A UNISON framework for analyzing alternative strategies of IC final testing for enhancing overall operational effectiveness," International Journal of Production Economics, Vol. 107, No. 1, pp.20-30.
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