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研究生:蘇昶嘉
研究生(外文):Su, Chang-Chia
論文名稱:利用固相磊晶的方式形成磊晶的N型錫化鍺並進行費米能階去釘札研究
論文名稱(外文):Investigation of Fermi Level Depinning on Epitaxial N-type GeSn Film Formed by Solid Phase Epitaxy
指導教授:巫勇賢
指導教授(外文):Wu, Yung-Hsien
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:58
中文關鍵詞:費米能階去釘札
外文關鍵詞:Fermi level depinning
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此文中,我們將探討費米能接釘札(Fermi-level pinning)在n型錫化鍺(GeSn)基板上的現象。我們首先分析了金屬/錫化鍺/鍺的接面特性,發現其金屬-半導體接觸時的接面會產生非常高的蕭基能障(Schottky barrier),若我們將其運用到電晶體的源極和汲極(Source/Drain)上,這個蕭基能障高度將影響電晶體的操作特性。因此在這篇論文中我們分別使用了CF4、O2以及NH3電漿,使錫化鍺與這些電漿產生反應,藉此產生一層抗釘札層(depinning layer),藉此達到去除費米能接釘札的效應(Fermi level depinning),其中氧氣電漿處理的結果最為顯著,蕭基能障高度從原本的0.63 eV下降到0.12 eV。除此之外,我們也同時運用了Germanide的方式來使源極與汲極達到歐姆接觸。在本研究中使用的金屬為鐿(Yb)並使用兩種沉積方式來形成Germanide,分別是以二氧化矽覆蓋(SiO2 capping)以及錫化鍺堆疊(GeSn capping)的方式來進行,並在沉積薄膜之後使用快速熱退火的處理,藉此形成Yb stanogermanide,而實驗的結果發現兩種方式都能成功地達到歐姆接觸,其中由於錫化鍺堆疊的方式可以成長出較厚的Yb stanogermanide,因此可以達到更高的電流密度。根據先前介紹的方式可以得知電漿處理以及Germanide的方式都可以成功地達到費米能接去釘札的效應,相信將此運用於MOSFET的Source/Drain上會使元件達到更好的特性。
Processes that achieve FL depinning for metal/n-Ge1-xSnx (1019 cm-3) contact were proposed for different technologies. For typical metal contact, O2 plasma treatment on Ge1-xSnx surface prior to metal contact is a more effective way for the purpose than other treatments since the formed GeSnOx has the desirable EG, ΔEc and κ value with the capability to passivate interfacial dangling bonds. For those require stanogermanide, YbGe1-xSnx formed by annealing of GeSn-capped Yb also exhibits ohmic conduction behavior due to interface states suppression. Both processes obtain low ρc of ~10-7 Ω-cm2 and ΦBN of ~0.1 eV, empowering next-generation GeSn technology.
總目錄
摘要 i
Abstract ii
致謝 iii
總目錄 iv
表目錄 vi
圖目錄 vii

第一章 序論 1
1-1 研究背景 1
1-2 GeSn能帶機制 2
1-3 GeSn接面 3
1-4 費米能階釘札 (Fermi level pinning) 4
1-5 研究動機 5
1-6 論文結構 6

第二章 文獻回顧 11
2-1 以分子束磊晶法 (Molecular beam epitaxy) 製作GeSn 11
2-2 以固相磊晶法 (Solid phase epitaxy) 製作GeSn 12
2-3 加入絕緣層之方式-Ultra thin film 19
2-4 利用電漿處理之方式-Plasma treatment 22
2-5 利用接面金屬化之方式-Germanide 23
2-6 利用離子佈植之方式-Ion implantation 25

第三章 實驗規劃原理及製作 27
3-1 GeSn/n-Ge 基板之製作 27
3-2 Al/Depinning layer/GeSn/n-Ge substrate 元件之製作 28
3-3 Yb stanogermanide/GeSn/n-Ge substrate 元件之製作 28

第四章 結果與討論 37
第一部分: Al/Depinning layer/GeSn/n-Ge substrate 元件之特性討論 37
4-1 電壓電流特性分析 37
4-2 蕭基能障高度分析 38
4-3 X射線光電子能譜分析 (X-ray Photoelectron Spectroscopy) 38
4-4 接觸電阻分析 (TLM Measurement) 39
第二部分: Yb stanogermanide/GeSn/n-Ge substrate 元件之特性討論 46
4-5 電壓-電流特性討論 - SiO2 capping 46
4-6電壓-電流特性討論 – GeSn capping 46
4-7 接觸電阻與蕭基能障高度比較 47
4-8 X射線繞射分析 (X-ray Diffraction) 47
4-9 穿透式電子顯微鏡分析 (Transmission Electron Microscopy) 48
第五章 結果與未來展望 52
參考文獻 54

第一章
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[1.2] J. D. Sau, and M. L. Cohen, “Possibility of increased mobility in Ge-Sn alloy system,” Phys. Rev. B, vol. 75, pp. 045208, 2007
[1.3] S. Gupta, B. Vincent, B. Yang, D. Lin, F. Gencarelli, J.-Y. J. Lin, R. Chen1, O. Richard, H. Bender, B. Magyari-Köpe, M. Caymax, J. Dekoster, Y. Nishi, and K. C. Saraswat, “Towards high mobility GeSn channel nMOSFETs: improved surface passivation using novel ozone oxidation method,” in Proc. IEEE IEDM, pp. 375-378, 2012
[1.4] G. Han, S. Su, L. Wang, W. Wang, X. Gong, Y. Yang, Ivana, P. Guo, C. Guo, G. Zhang, J. Pan, Z. Zhang, C. Xue, B. Cheng, and Y. C. Yeo, “Strained germanium-tin (GeSn) n-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer,” in Proc. Symp. VLSIT, pp. 97-98, 2012
[1.5] S. Gupta, Y. C. Huang, Y. Kim, E. Sanchez, and K. C. Saraswat, “Hole mobility enhancement in compressively strained Ge0.93Sn0.07 pMOSFETs,” IEEE Electron Device Lett., vol. 34, no. 7, pp. 831-833, 2013
[1.6] L. Wang, S. Su, W. Wang, X. Gong , Y. Yang, P. Guo, G. Zhang, C. Xue, B. Cheng, G. Han, Y. C. Yeo, “Strained germanium–tin (GeSn) p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with ammonium sulfide passivation,” Solid-State Electronics, vol. 83, pp. 66-70, 2013
[1.7] S. Gupta, R. Chen, B. M. Kope, H. Lin, B. Yang, A. Nainani, Y. Nishi, J. S. Harris,
and K. C. Saraswat, “GeSn technology: extending the Ge electronics roadmap,” in Proc. IEEE IEDM, pp. 398-401, 2011
[1.8] Y. Yang, G. Han, P. Guo, W. Wang, X. Gong, L. Wang, K. L. Low, and Y. C. Yeo, “Germanium–tin p-channel tunneling field-effect transistor: device design and technology demonstration,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4048-4056, 2013
[1.9] R. R. Lieten, J. W. Seo, S. Decoster, A. Vantomme, S. Peters, K. C. Bustillo,
E. E. Haller, M. Menghini, and J.-P. Locquet, “Tensile strained GeSn on Si by solid phase epitaxy,” Appl. Phys. Letters., vol. 102, no. 5, pp. 052106, 2013
[1.10] S. Gupta, R. Chen, B. Vincent, D. H. C. Lin, B. Magyari-Köpea, M. Caymax, J. Dekoster, J. Harris, Y. Nishi, and K. C. Saraswat, “GeSn Channel n and p MOSFETs” ECS Trans, vol. 50, no. 9, pp. 937-941, 2012.
[1.11] Q. Zhang, N. Wu, T. Osipowicz, L. K. Bera, and C. Zhu,“Formation and Thermal Stability of Nickel Germanide on Germanium Substrate,” Japanese Journal of Applied Physics, 44, pp. L1389-L1391, 2005
[1.12] A. Dimoulas, P. Tsipas, and A. Sotiropoulos, “Fermi-level pinning and charge neutrality level in germanium,” Applied Physics Letters, vol. 89, pp. 252110, 2006
[1.13] L. Lin, Y. Guo and J. Robertson,“Metal silicide Schottky barriers on Siand Ge show weaker Fermi levelpinning” Applied Physics Letters, vol. 101, pp. 052110, 2012
[1.14] M. Kobayashi, A. Kinoshita,K. Saraswat, H.S.P. Wong and Y. Nishi, “Fermi level depinning in metal/Ge Schottky junction for metal source/drainGe metal-oxide-semiconductor field-effect-transistor application” Journal of Applied Physics, vol. 105, pp. 023702, 2009
[1.15] R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs,“Ohmic contact formation on n-type Ge,” Applied Physics Letters, vol. 92, pp. 022106, 2008
[1.16] N. Tomonori, K. Koji and T. Akira, “A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film,” Applied Physics Express, vol. 1, pp. 051406, 2008
[1.17] D. Connelly, C. Faulkner, D. E. Grupp and J. S. Harris, “A New Route to Zero-Barrier MetalSource/Drain MOSFETs,” IEEE Transactions on Nanotechnology, vol. 3, pp. 98-104, 2004


第二章
[2.1] G. Han, S. Su, C. Zhan, Q. Zhou, Y. Yang, L. Wang, P. Guo, W. Wei, C. P. Wong, Z. X. Shen, B. Cheng, and Y. C. Yeo, “High-mobility germanium-tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules,” in Proc. IEEE IEDM, pp. 402-404, 2011
[2.2] C. W. Lee, Yung-Hsien Wu, Ching-Heng Hsieh and Chia-Chun Lin.,“Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb2O3-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness,”Appl. Phys. Letters., vol. 105, no. 20, pp. 203508-1-203508-4, 2014
[2.3] D. R. Gajula, P. Baine, M. Modreanu, P. K. Hurley, B. M. Armstrong, “Fermi level de-pinning of aluminium contacts to n-type germanium using thin atomic layer deposited layers”, Applied Physics Letters, vol. 104, pp. 012102-1-012102-4, 2014
[2.4] Jia-Rong Wu, Yung-Hsien Wu, Chin-Yao Hou, Min-Lin Wu, Chia-Chun Lin, and Lun-Lun Chen, “Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions,” Applied Physics Letters., vol. 99, pp. 253504-1-203504-3, 2011
[2.5] Ravi Kesh Mishra, Udayan Ganguly, Swaroop Ganguly, Saurabh Lodha, “Nickel germanide with rare earth interlayers for Ge CMOS applications,” Apply Materials. Inc., pp. 978-1-4673-2523-3, 2013
[2.6] Yi Tong, Genquan Han, Bin Liu, Yue Yang, Lanxiang Wang, Wei Wang, and Yee-Chia Yeo, “Ni(Ge1−xSnx) Ohmic Contact Formation on N-Type Ge1−xSnx Using Selenium or Sulfur Implant and Segregation,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 746-752, 2013


第五章
[5.1] K. Martens, A. Firrincieli†, R. Rooyackers, B. Vincent, R. Loo, S. Locorotondo, E. Rosseel, T. Vandeweyer, G. Hellings, B. De Jaeger, M. Meuris, P. Favia, H. Bender, B. Douhard, J. Delmotte, W. Vandervorst†, E. Simoen, G. Jurczak, D. Wouters†, J. A. Kittl, “Record low contact resistivity to n-type Ge for CMOS and Memory Applications” , IEEE IEDM, 10-428, pp.18.4.1-18.4.4, 2010
[5.2] J. Y. Jason Lin, “Reduction in Specific Contact Resistivity to n+ Ge Using TiO2 Interfacial Layer”, IEEE Electron Device Letters, vol. 33, no. 11, pp.1541-1543, 2012
[5.3] P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M. C. Abraham, S. Kapadia, U. Ganguly, and S. Lodha, Symp. VLSI Technol., Dig. Tech, pp. 83–84, 2012
[5.4] Gwang-Sik Kim, Seung-Hwan Kim, Jeong-Kyu Kim, Changhwan Shin, Jin-Hong Park, Krishna C. Saraswat, Byung Jin Cho, and Hyun-Yong Yu, “Surface Passivation of Germanium Using SF6 Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET”, IEEE Electron Device Letters, vol. 36, no. 8, pp. 745-747, 2015

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