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研究生:張佑碩
研究生(外文):Chang, Yu Shuo
論文名稱:垂直式堆疊多晶矽奈米薄片電晶體之研究
論文名稱(外文):Study of Vertically Stacked Poly-Si Nanosheet Field-Effect-Transistor
指導教授:吳永俊吳永俊引用關係
指導教授(外文):Wu, Yung Chun
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:英文
論文頁數:58
中文關鍵詞:垂直堆疊結構奈米薄片多晶矽通道
外文關鍵詞:vertically stacked structurenanosheetPoly-Si channel
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隨著可攜式電子產品市場需求,產品功能不斷擴張,並強調體積小及重量輕等要求,經濟市場及業界相互競爭下,驅使電子業做出更好的產品,造成產品中的電晶體需朝著低成本高密度發展,且不斷微縮以符合市場需求,而在微縮過程中元件製程和物理的限制越來越多,增加設計電晶體的困難,無論是元件結構上的短通道效應或是製程上的挑戰都是很重要的研究議題。
本篇論文開發出垂直堆疊結構奈米薄片電晶體,能應用在未來三維堆疊積體電路中,來提高電晶體密度以延續Moore’s law,極具學術與產業界應用價值,此篇研究中為是元件製程、基礎元件特性分析、模擬物性分析,在堆疊結構製程上,我們提出使用氧化薄化的方式對多晶矽通道進行薄化,形成較薄主動層,由於薄化可使通道多晶晶粒大小減小以及缺陷降低,可得到近似單晶的通道。在基礎元件特性分析中,第一部分則是比較堆疊結構與一般結構的差異,堆疊結構展現出較佳的電性,由於堆疊結構的電阻可視為並聯,串聯電阻較小,提升了約4.36倍的驅動電流及有較高的開關電流比(Ion/Ioff current ratio>108),並預期使開電流隨著元件層數而增加,但仍可維持一樣好的電特性,第二部分將探討隨著元件尺寸變寬對堆疊結構的電性影響。另外模擬物性分析中,我們使用Sentaurus TCAD模擬軟體與實際數據作分析比較,驗證模擬結果與實驗數據相符。
此篇研究中提出垂直堆疊結構奈米薄片電晶體有良好的電特性,因此有機會提供下個世代互補金氧半場效應電晶體(CMOS)的解決方法,並應用在未來三維堆疊結構與系統晶片(SoC)上。

The market demand for portable electrical equipments increase dramatically year by year., emphasizing on multifunctional, small size, light weight, etc. Under keen mutual competition environment of economic market and electronic industries, it has triggered electronic industries to improve their products to develop toward low cost, high density and scale down to react to the rapid demand in the market. Nevertheless, the expectation of scaling transistors suffered more and more difficult to design, whether the short channel effect in devices or the challenge of fabrication process are very vital research topics.
In this thesis, we successfully demonstrate the stacked nanosheert(NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law. It may offer valuable information with regard to their practical industry and academic applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. In the fabrication process, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked NS VM-FET and conventional NS IM-FET. The stacked structure exhibits the better characteristics owing to due to the parallel resistance, resulting in smaller total resistance and improved around 4.36 times current drivability and higher ON/OFF current ratio up to 108. The 3D stacked layer can increase on-state current and maintain low leakage current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics
As a result, we proposed the stacked NS VM-FET has better electrical characteristics. Additionally, it may offer a possible next-generation CMOS device solution and be applied in advanced system-on-chip and 3D stacked IC applications.

Contents
中文摘要.........................................i
Abstract......................................................................................................................................iii
Acknowledge..............................................................................................................................v
Contents....................................................................................................................................vii
Table Captions.........................................................................................................................viii
Figure Captions ix
Chapter 1.................................................................................................................................- 1 -
Introduction.............................................................................................................................- 1 -
1-1 Challenge of Scaling Down the Device - 1 -
1-2 Polycrystalline silicon Channel - 4 -
1-3 Ultra Thin Body of Semiconductor Device - 6 -
1-4 Design consideration of multiple-gate device - 9 -
1-5 Motivation - 14 -
1-6 Organization of This Dissertation - 18 -
Chapter 2...............................................................................................................................- 19 -
Conventional MOSFET - 19 -
2-1 Basic Principle of MOSFT - 19 -
2-2 MOS Parameters Extraction - 21 -
A. Threshold voltage (Vth) - 21 -
B. Subthreshold swing (SS) - 22 -
C. ON/OFF current ratio(Ion/Ioff) - 22 -
D. Drain Induced Barrier Lowering(DIBL) - 22 -
E. Gate induced Drain Leakage(GIDL) - 23 -
Chapter 3...............................................................................................................................- 25 -
Device Fabrication - 25 -
3-1 Device Fabrication Process - 25 -
3-2 Images Analysis - 28 -
3-2-1 SEM image of device structure - 28 -
3-2-2 SIMS profile of device structure - 29 -
3-2-3 TEM image of device structure - 30 -
Chapter 4...............................................................................................................................- 33 -
Characteristics Analysis - 33 -
4-1 Device Electrical Analysis - 33 -
4-2 Device Simulation - 46 -
4-2-1 Device Structure and Parameters - 46 -
4-2-2 Device Simulation Analysis - 48 -
4-2-3 Comparison of Oxide Thickness (Interlayer) - 53 -
Chapter 5...............................................................................................................................- 54 -
Conclusion............................................................................................................................- 54 -
Reference..............................................................................................................................- 55 -


Chapter 1

[1-1] W. Arden, M. Brillouet, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf, More-than-Moore, White Paper. [Online]
Available: http://www.itrs.net/Links/2010ITRS/IRC-ITRS-MtM-v2%203.pdf
[1-2] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. Pin Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu," A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," in IEDM Tech. Dig., 2006, pp. 507-510.
[1-3] H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., pp. 131–132, 2010.
[1-4] R. Ishihara , J. Derakhshandeh, M.R. Tajari Mofrad, T. Chen, N. Golshani, C.I.M. Beenakker," Monolithic 3D-ICs with single grain Si thin film transistors," Solid State Elect., vol. 71, pp. 80-87, Feb. 2012.
[1-5] C. Hu, Modern semiconductor devices for integrated circuits: Prentice Hall, pp.295-296, 2010
[1-6] C. Hu, "SOI (silicon-on-insulator) for high speed ultra large scale integration," Japanese journal of applied physics, vol. 33, p. 365, 1994.
[1-7] B. Yu, Y. Tung, S. Tang, E. Hui, T. King, and C. Hu, "Ultra-thin-body Silicon-on-insulator MOSFET’s for terabit-scale integration," in Proc. Int. Semiconductor Device Research Symp, 1997, pp. 623-626


[1-8] S.-H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J.-Y. Ahn, H. Choi, et al., "Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash," in Reliability Physics Symposium (IRPS), 2011 IEEE International, 2011, pp. 2E. 4.1-2E. 4.4.
[1-9] J.-P. Colinge, FinFETs and other multi-gate transistors vol. 73: Springer, 2008.
[1-10] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, J. Y. Chin, P. H. Yeh, L. W. Feng, S. M. Sze, C. Y. Chang, and C. H. Lien, "Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics," Appl. Phys. Lett., vol. 91, pp. 193103, Nov. 2007.
[1-11] J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani," Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell," IEEE Electron Device Lett., vol. 29, no. 5, pp. 518-521, May 2008.
[1-12] B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, et al., "Vertically integrated multiple nanowire field effect transistor," Nano letters, vol. 15, pp. 8056-8061, 2015.
[1-13] H.-B. Chen. Y.-C. Cheng, C.-Y. Chang, C.-H. Cheng, Y.-J. Shih, and Y.-C. Wu, "A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs," presented at the 2016 Symposia on VLSI Technology and Circuits, Hilton Hawaiian Village, Honolulu, HI
[1-14] S.-D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M.-H. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, 2015, pp. 1-3.
[1-15] J. Kim, A. Hong, S. M. Kim, E. Song, J. H. Park, J. Han, S. Choi, D. Jang, J. T. Moon, and K. Wang, “Novel Vertical-Stacked-ArrayTransistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (Solid State Drive),” in VLSIT’09, 2009, pp. 186 –187.
Chapter 2
[2-1] S. M. SZE, KWOK K. NG, “Physics of Semiconductor Devices” 3rd Ed., ch. 6, New Jersey: Wiley-InterScience, 2007.
[2-2] J. E. Lilienfeld, "Method and Apparatus for Controlling Electric Current," U.S. Patent 1 745 175, Jan., 1930.
[2-3] J. E. Lilienfeld, "Amplifier for Electric Current," U.S. Patent 1 877 140, Sep., 1932.
[2-4] J. E. Lilienfeld, "Device for Controlling Electric Current," U.S. Patent 1 900 018, Mar., 1933.
[2-5] W. Shockley and G. L. Pearson, “Modulation of Conductance of Thin Films of Semiconductors by Surface Charges,” Phy. Rev., vol. 74, pp. 232, Jul., 1948.
[2-6] D. Kahng, “A Historical Perspective on the Development of MOS Transistors and Related Devices,” IEEE Trans. Electron Devices, vol. ED-23, no. 7, pp. 655–657, Jul., 1976.
[2-7] C. T. Sah, “Evolution of the MOS Transistor-From Conception,” Proc. IEEE, vol. 76, no. 10, pp. 1280–1326, Oct., 1988.
[2-8] C. Hu, Modern semiconductor devices for integrated circuits: Prentice Hall, ch. 6, 2010
[2-9] TCAD Sentaurus Device, Synopsys SDevice Ver.J-2014.09, Synopsys, Inc., Mountain View, CA, USA
[2-10] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327, 2003.
[2-11] J.-P. Colinge and C. A. Colinge, Physics of semiconductor devices: Springer Science & Business Media, 2005.,




Chapter 4
[4-1] M.-S. Yeh,Y.-C Wu, M.-H. Wu, M.-H. Chung, Y.-R.Jhan, and M.-F. Hung, “Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure,”IEEE Electron Device Lett.,vol. 36, no. 2, pp. 150–152, Feb. 2015.
Chapter 5
[5-1] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, H. M. Choi, K. Hwang, Y. Ko, and C. J. Kang, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash,” in Proc. IEEE International. Reliability Physics Symposium, Apr. 2011, pp. 126–129.

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