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研究生:李典勇
研究生(外文):Li, Dian-Yong
論文名稱:接觸蝕刻停止層與矽鍺通道之機械性質對具偽閘極陣列N型短通道奈米元件之影響
論文名稱(外文):The Effect of Contact-Etch-Stop-Layer and Si1-xGex Channel Mechanical Properties on Nano-Scaled Short Channel NMOSFETs with Dummy Gate Array
指導教授:劉傳璽劉傳璽引用關係鄭慶民鄭慶民引用關係李昌駿李昌駿引用關係
指導教授(外文):Liu, Chuan-HsiCheng, Ching-minLee, Chang-Chun
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:機電工程學系
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
論文頁數:72
中文關鍵詞:矽鍺通道接觸蝕刻停止層有限元素分析偽閘極陣列
外文關鍵詞:SiGe channelCESLFinite element analysisDummy gate array
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本研究旨在分析於不同閘極寬度、偽閘極陣列數量,以及不同偽閘極間Poly-to-Poly距離的情形下,具矽鍺通道結構N型偽閘極陣列電晶體之應力分佈與性能表現。而經研究後發現,藉由接觸蝕刻停止層結合矽鍺通道結構之應變工程技術可有效提升元件性能。將矽鍺通道因晶格不匹配而產生之應力,與接觸蝕刻停止層之內應力結合,組成多重應力源結構,並藉由三維有限元素分析軟體,模擬分析此結構於N型電晶體內之通道應力分佈。使用3.0 GPa之拉伸應力,做為接觸蝕刻停止層之內應力,並將25 % 做為矽鍺通道之鍺莫耳分率用以模擬分析。分別對偽閘極陣列數量與偽閘極間Poly-to-Poly距離進行調變,結果顯示當電晶體閘極寬度較寬時,單根閘極之載子遷移率比多根偽閘極陣列之情形更為優異,而較短的Poly-to-Poly結構之載子遷移率會比較長的Poly-to-Poly結構更為優異,而最佳之電晶體特性表現將會發生在閘極寬度為100 nm之結構尺寸,約能比傳統電晶體提升40%之效能。
The study focused on analyzing the stress distribution and performance of N-type transistors with silicon germanium channel and dummy gate arrays structure under different gate widths, numbers of dummy gate arrays, and gate pitch (Poly-to-Poly) spacings. Research found by using the strained engineering in contact etch stop layer (CESL) combined with silicon germanium channel structure can be efficiently utilized to enhance the performance of devices. In this research, we have combined the stress from silicon germanium channel lattice mismatch and contact etch stop layer, and simulated the channel stress distribution of this structure in N-type transistors via three-dimensional finite element analysis software. The intrinsic CESL stress considered in this study was tensile (3.0 GPa) (t-CESL). A 25% germanium mole fraction utilized in the Si1-xGex channel was selected to carefully analyze its impact on the Si1-xGex channel. Then we changed the number of dummy gate arrays and the Poly-to-Poly gap between dummy gates. The result shows that with a wider gate width, the carrier mobility of single gate structure is better than the plural dummy gate array, and the carrier mobility of shorter Poly-to-Poly structure is better than longer Poly-to-Poly structure. The best performance of transistors would occur in a 100 nm gate width and enhance 40% compared with the traditional transistors.
第一章 緒論 1
1.1 前言 1
1.2 金氧半場效電晶體及應變矽工程技術 1
1.3 實驗方向 1
第二章 文獻探討 3
2.1 金氧半場效電晶體 4
2.1.1 背景 4
2.1.2 基本結構 5
2.1.3 工作原理、輸出特性與轉移特性 7
2.1.4 電晶體性能 13
2.1.5 載子遷移率 14
2.2 應變工程技術 16
2.2.1 應力與應變 16
2.2.2 壓阻效應 22
2.3 接觸蝕刻停止層與矽鍺通道結構 24
2.3.1 具接觸蝕刻停止層應力源之結構 24
2.3.2 具矽鍺通道之結構 34
第三章 實驗步驟與方法 40
3.1 有限元素分析 40
3.1.1 前言 40
3.1.2 元素單元類型 43
3.1.3 模型簡化與平面應力、平面應變 46
3.2 模擬步驟流程 49
3.2.1 材料特性 50
3.2.2 模擬方法與模型建立 51
3.2.3 參數調變與負載設定 55
第四章 結果與討論 58
4.1具矽鍺通道結構結合接觸蝕刻停止層應力源之N型電晶體驗證 58
4.1.1 具矽鍺通道結構之驗證 58
4.1.2 具矽鍺通道結構與接觸蝕刻停止層應力源之驗證 60
4.2 具矽鍺通道結構結合接觸蝕刻停止層應力源之偽閘極陣列於閘極寬度調變之研究 62
4.2.1 偽閘極陣列數量之調變 62
4.2.2 偽閘極陣列間Poly-to-Poly距離之調變 64
第五章 結論與未來展望 66
5.1 應變工程技術用於提升電晶體性能 66
5.2 未來展望 67
參考文獻 68


參考文獻
[1] 工研院產業經濟與趨勢研究中心及資策會資訊市場情報中心,2015年台灣重要產業技術發展藍圖I,工研院IEK,2008。
[2] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz and M. Radosavljevic, “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications”, IEEE Transactions on Nanotechnology, Vol. 4, No. 2, pp. 153-158, 2005.
[3] S. E. Thompson and S. Parthasarathy, “Moore’s Law: The Future of Si Microelectronics”, Materialstoday, Vol. 9, No.6, pp. 20-25, 2006.
[4] 劉傳璽、陳進來,第三版,半導體物理元件與製程-理論與實務,五南文化出版社,2006。
[5] M. Quirk and J. Serda, Semiconductor Manufacturing Technology, Pearson, 2011.
[6] U. K. Mishra and J. Singh, Semiconductor Device Physics and Design, Springer, 2008.
[7] S. M. Sze, Semiconductor Devices-Physics and Technology, 2nd edition, Wiley, 2001.
[8] M. Khan, T. Muntasir, A. Rahman, U. Acharjee and M. Layek, “Multiple Polynomial Regression for Modeling a MOSFET in Saturation to Validate the Early Voltage”, IEEE Symposium on Industrial Electronics and Applications, pp. 261-266, 2011.
[9] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi and J. C. Lee, “Electrical Characteristics of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric”, IEEE Electron Device Letters, Vol. 21, No. 4, pp. 181-183, 2000.
[10] H. S. Choi, K. S. Seol, D. Y. Kim, J. S. Kwak, C. S. Son and I. H. Choi, “Thermal Treatment Effects on Interfacial Layer Formation”, Vacuum, Vol. 80, pp. 310-316, 2005.
[11] J. Robertson and P. W. Peacock, “Electronic Structure and Band Offsets of High-Dielectric-Constant Gate Oxides”, Materials Research Society, Vol. 27, pp. 217-221, 2002.
[12] 鄭晃忠、劉傳璽,新世代積體電路製程技術,東華書局,2011。
[13] R. C. Hibbeler, Mechanics of Materials, 8th edition, Pearson, 2011.
[14] F. P. Beer, E. R. Johnston, J. T. DeWolf and D. F. Mazurek, “Mechanics of Materials, 7th Edition”, McGraw-Hill.
[15] ASTM Standard E8-96a. “Standard Test Methods for Tension Testing of Metallic Materials. In: Annual Book of ASTM Standards”, West Conshohocken (PA): American Society for Testing and Materials, pp. 56-76, 1997.
[16] W. Thomson (Lord Kelvin), “On the Electro-Dynamic Qualities of Metals”, Proceedings of the Royal Society of London, Vol. 8, pp. 546-550, 1857.
[17] C. S. Smith, “Piezoresistance Effect in Germanium and Silicon”, Physical Review, Vol. 94, No 1, pp. 42-49, 1954.
[18] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr and Y. El-Mansy, “A Logic Nanotechnology Featuring Strained-Silicon”, IEEE Electron Device Letters, Vol. 25, No. 4, pp. 191-193, 2004.
[19] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr and Y. El-Mansy, “A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Transactions on Electron Device, Vol. 51, No. 11, pp. 1790-1797, 2004.
[20] 莊達人,VLSI 製造技術,高立出版社,1999。
[21] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoch and T. Horiuchi, “Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design”, IEDM Technical Digest, pp. 247-250, 2000.
[22] T. Ghani, M. Armstrong, C. Auth, M. Giles, K. Mistry, A. Murthy, S. Thompson and M. Bohr, “Uniaxial Strained Silicon CMOS Devices for High Performance Logic Nanotechnology”, Portland Technology Development, TCAD, Intel Corporation, Hillsboro, OR.
[23] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo and C. Hu, “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering”, IEDM Technical Digest, pp. 73-76, 2003.
[24] A. Shimizu, K. Hachimin, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato and F. Ootsuka, “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, IEDM Technical Digest, pp. 433-437, 2001.
[25] S. Ito, H. Namba, T. Hirata, K. Ando, S. Koyama, N. Ikezawa, T. Suzuki, T. Saitoh and T. Horiuchi, “Effect of Mechanical Stress Induced by Etch-Stop Nitride Impact on Deep-Submicron Transistor Performance”, Microelectronics Reliability, Vol. 42, pp. 201–209, 2002.
[26] G. Eneman, P. Verheyen, A. D. Keersgieter, M. Jurczak and K. D. Meyer, “Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study”, IEEE Transactions on Electron Device, Vol. 54, No. 6, pp. 1446-1453, 2007.
[27] M. C. Wang, H. C. Yang, W. S. Liao, H. Y. Yang, Y. Y. Hoe, K. H. Lin, S. Y. Chen, “CESL Deposition Promoting n/p MOSFETs under 45-nm-Node Process Fabrication”, IEEE International Symposium on Next-Generation Electronics, pp. 17-20, 2010.
[28] Y. C. Yeo, Q. Lu, T. J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, “Enhanced Performance in Sub-100 nm CMOSFETs Using Strained Epitaxial Silicon-Germanium”, International Electron Devices Meeting, pp. 753-756, 2000.
[29] 劉晉奇、褚晴暉,有限元素分析與ANSYS的工程應用,滄海書局,2006。
[30] 陳精一,ANSYS 7.0電腦輔助工程實務分析,全華出版社,2003。
[31] S. Moaveni, “Finite Element Analysis: Theory and Application with ANSYS”, Pearson Education/Prentice Hall, 2005.
[32] K. N. Chiang, C. H. Chang and C. T. Peng, “Local-Strain Effects in Si/SiGe/Si Islands on Oxide”, Applied Physics Letters, Vol. 87, No. 19, pp. 191901-1-191901-3, 2005.
[33] G. Eneman, E. Simoen, P. Verheyen and K. D. Meyer, “Gate Influence on the Layout Sensitivity of Si1−xGex S/D and Si1−yCy S/D Transistors Including an Analytical Model”, IEEE Transactions on Electron Device, Vol. 55, No. 10, pp. 2703–2711, 2008.
[34] C. C. Lee, H. C. Cheng, H. W. Hsue, Z. H. Chen, H. H. Teng and C. H. Liu, “Mechanical Property Effects of Si1-xGex Channel and Stressed Contact Etching Stop Layer on Nano-Scaled N-Type Metal–Oxide–Semiconductor Field Effect Transistors” Thin Solid Films, Vol. 557, pp. 316–322, 2014.

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