臺灣博碩士論文加值系統

本論文為設計5GHz低功耗之射頻接收機前端電路，其中電路包含電壓控制振盪器、低雜訊放大器和混頻器，使用國家晶片系統設計中心所提供之Agilent Advanced Design System(ADS)軟體進行電路模擬，電路中元件均為TSMC 0.18 m 1P6M CMOS Mixed-Signal模型。

第一顆晶片是電壓控制振盪器(VCO)，使用互補式為主架構，結合NMOS與PMOS的優點，使用LC-tank架構和CMOS形式達到低功耗和減少晶片面積以設計電壓控制振盪器。測量的結果，電路在4.6GHz的振盪頻率時，可調頻率範圍為600MHz，相位雜訊在1MHz偏移頻率下為-111.2dBc/Hz，此電路FOM值為-181.7 dBc/Hz，功率消耗為2.1mW，晶片面積為0.852*0.65 mm2。

第二顆晶片是低雜訊放大器(LNA)，主架構是疊接式架構並在電路中加入一組電流鏡來達到低功耗，測量的結果，顯示電路在5GHz的振盪頻率時，最大增益(S21)為8.75dB，輸入端反射損耗(S11)與輸出端反射損耗(S22)分別為-13dB和-9dB，最小雜訊增益為5.8dB，此電路P1dB值與IIP3值分別為-20 dBm與-15dBm，在輸入電壓為1V時，功率消耗為4.2mW，此低雜訊放大器晶片面積為1.5*1.0 mm2。

第三顆晶片是混頻器(Mixer)，採用單端平衡式架構，在轉導級增加兩顆電晶體，使其操作在飽和與線性區之間，類似成一顆等效電阻，增加線性度，在雜訊部分使用雜訊抵銷架構，使其降低雜訊。模擬結果顯示，在5GHz時，轉換增益為8.4dB，雜訊指數為25dB，P1dB為-16dBm，IIP3為-10dBm，在輸入電壓1V時，功率消耗為8mW，晶片面積為1.3*0.75 mm2

In this thesis, we design 5GHz low power RF receiver font-end circuits, which consist of a voltage-controlled oscillator (VCO), a low noise amplifier (LNA) and a mixer. The circuits are simulated with the Agilent Advanced Design System (ADS) software supported by National Chip Implementation Center (CIC), and circuit components use the TSMC 0.18 um 1P6M CMOS Mixed-Signal models.

The first chip is a voltage-controlled oscillator (VCO) which uses the complementary architecture as the main feature to combine the advantages of NMOS and PMOS. The circuit uses LC tank and CMOS structure to achieve low power and decrease the wafer area. The measurement results show that the tuning range is 600MHz, the phase noise is -111.2 dBc/Hz at 1MHz offset from the carrier frequency of 4.6 GHz. The FOM can achieve -181.7 dBc/Hz, the power consumption is 2.15mW, and the chip area is 0.852*0.65 mm2.

The second chip is a low noise amplifier (LNA) which adopts cascode architecture and current mirror to achieve the low power. The measurement results show that the maximum power gain (S21) is 8.75 dB. The input reflection coefficient S11 and output reflection coefficient S22 are lower than -13 dB and -9 dB, respectively. The minimum noise figure is 5.8 dB from the carrier frequency of 5 GHz. The P1dB and input third-order intercept point (IIP3) are -20dBm and -15dBm. The power consumption is 4.2mW at 1V supply voltage. This LNA occupies an area of 1.5*1.0 mm2.

The third chip is a mixer with the single-balanced architecture. In the transconductance stage, we add two transistors operating between the saturation and linear region which are equivalent to a resistor to improve the linearity. In noise part, we use noise cancellation technique to reduce the noise. The simulation results show that the conversion gain is 8.4dB, the noise figure is 25dB, the P1dB is -16dBm, the IIP3 is -10dBm from the carrier frequency of 5 GHz. The power consumption is 8mW at 1V supply voltage, and the chip area is 1.3*0.75 mm2.

摘要...........................................I
Abstract......................................II
目錄..........................................III
圖目錄.........................................V
表目錄........................................VII
第一章 緒論..................................1
1.1 研究動機.................................1
1.2 射頻接收機架構簡介紹.......................1
1.3 IEEE 802.11AC 系統介紹....................4
1.4 論文架構..................................5
第二章 電壓控制振盪器..........................6
2.1 電壓控制振盪器簡介.........................6
2.2 電壓控制振盪器原理與架構....................6
2.2.1 回授分析法..............................6
2.2.2 負電阻分析法............................7
2.2.3 環形振盪器 (Ring Oscillator)............8
2.2.4 LC諧振振盪器 (LC-tank Oscillator........9
2.3 電壓控制振盪器重要參數.....................11
2.3.1 相位雜訊 (Phase Noise)..................11
2.3.2 可調頻率範圍 (Tuning Range).............12
2.3.3 輸出功率 (Output Power).................13
2.3.4 消耗功率 (Power Consumption)............13
2.4 低功耗電壓控制振盪器設計....................13
2.4.1 電路架構................................13
2.4.2 模擬結果................................16
2.4.3 量測結果................................26
2.4.4 結論....................................30
第三章 低雜訊放大器............................31
3.1 低雜訊放大器簡介...........................31
3.2 低雜訊放大器特性參數........................31
3.2.1 S參數 (S parameter).....................31
3.2.2 穩定度..................................33
3.2.3 雜訊指數................................35
3.2.4 1dB增益壓縮點...........................36
3.3 低雜訊放大器架構介紹.......................37
3.4 低功耗低雜訊放大器之設計....................39
3.4.1 電路架構................................40
3.4.2 模擬結果................................42
3.4.3 量測結果................................52
3.4.4 結論....................................55
第四章 混頻器.................................56
4.1 混頻器簡介................................56
4.2 混頻器原理................................57
4.3 混頻器架構................................60
4.3.1 被動式混頻器............................60
4.3.2 主動式混頻器............................60
4.4 混頻器重要參數............................62
4.4.1 轉換增益 (Conversion Gain).............62
4.4.2 輸入端三階交互調變交叉點 (IIP3)..........62
4.4.3 隔離度.................................63
4.5 低功耗混頻器設計..........................64
4.5.1 電路架構...............................64
4.5.2 模擬結果...............................67
4.5.3 結論...................................76
第五章 總結與未來展望..........................77
參考文獻........................................78

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