臺灣博碩士論文加值系統

在次世代無線通訊系統中，類比至數位轉換器必須操作在極高速的取樣頻率及低中解析度下。
本論文提出一個以40奈米CMOS一般製程，實現出六位元每秒四十五億次取樣的時間交錯連續漸進式類比至數位轉換器，藉由結合前端輸入緩衝器的架構及分組式技巧，有效地降低時間交錯式架構的輸入電容負載，並增加輸入訊號的可用安定時間，提出的16通道的時間交錯連續漸進式類比至數位轉換器得以達到高取樣速度及高輸入頻寬的表現。透過使用零交越 (zero-crossing) 偵測技巧，可以補償多通道間時間偏移的誤差，並透過數位校正處理多通道間的增益電壓及偏移電壓不匹配。在單通道方面，採用連續漸進式架構，並使用非同步處理及單向電容切換技巧使單通道具有高速度及高能量效率的特性。除此之外，任意選擇權重之電容陣列解決了單通道中比較器的動態偏移電壓的問題。
量測結果顯示，在每秒四十億的轉換，DNL和INL分別為+0.17/-0.29 LSB和+0.20/-0.18 LSB。在每秒四十五億的轉換及輸入頻率為一億赫茲下，SNDR和SFDR分別為32.15 dB和41.04 dB，在1.2 V的供應電壓下，功率消耗為24.9毫瓦，品質因數(FoM)為159 fJ/c.-s。全部的晶片面積大小為1.275 mm2，核心電路的面積是0.195平方毫米。

Analog-to-digital converter (ADC) has to operate at ultra-high speed with low to medium resolution in the next-generation wireless communication systems.
A 6-bit 4.5 GS/s time-interleaved SAR ADC in 40 nm CMOS general–process (GP) technology is proposed. By combining the front-end input buffers and the grouping technique into the time-interleaved architecture, the input capacitance effectively decreases and the available settling of input buffers increases. The proposed 16-channel time-interleaved SAR ADC achieves the performance of high-speed sampling rate and high input bandwidth. A zero-crossing detection technique is employed to correct timing skew among sub-ADCs. Gain and offset mismatches between sub-ADCs are calibrated in the digital domain. Asynchronous processing and monotonic capacitor switching technique used in the single-channel SAR ADC make the sub-ADC high speed and power-efficiency. Furthermore, AWCA technique solves the dynamic offset problem of the comparator in the sub-ADC.
The measurement results show that ADC exhibits DNL of +0.17/-0.29 LSB and INL of +0.20/-0.18 LSB at 4 GS/s with Fin of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB at 4.5 GS/s with Fin of 1 GHz. The power consumption is 24.9 mW at 1.2 V supply voltage. As a result, the FoM (Power/2ENOB/FS) is 159 fJ/conversion-step. The whole chip including pads occupies 1.275 mm2 while area of core circuit is 0.195 mm2.

致謝 III
摘要 IV
Abstract V
Contents VI
List of Figures X
List of Tables XIV
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Fundamentals of Analog to Digital Converter 4
2.1 Introduction 4
2.2 Performance Metrics 4
2.2.1 Static Performance 4
2.2.1.1 Offset and Gain Error 4
2.2.1.2 Differential and Integral Nonlinearities (DNL, and INL) 5
2.2.2 Dynamic Performance 6
2.2.2.1 Signal-to-Noise Ratio (SNR) 7
2.2.2.2 Total Harmonic Distortion (THD) 7
2.2.2.3 Spurious Free Dynamic Range (SFDR) 7
2.2.2.4 Signal-to-Noise and Distortion Ratio (SNDR) 8
2.2.2.5 Effective Number of Bits (ENOB) 8
2.2.2.6 Figure of Merit (FoM) 8
2.3 Architectures 9
2.3.1 Flash Architecture 9
2.3.2 Successive-Approximation-Register Architecture 10
2.3.1 Time-Interleaved Architecture 12
2.4 Error Sources and Calibrations in Time-Interleaved Architecture 14
2.4.1 Offset Mismatch and Calibration 14
2.4.2 Gain Mismatch and Calibration 17
2.4.1 Timing Skew Mismatch and Calibration 20
2.5 Summary 23
Chapter 3 Proposed Time-Interleaved SAR ADC 24
3.1 Introduction 24
3.2 Time-Interleaved ADC Architecture 24
3.2.1 One Rank Time-Interleaved Architecture 25
3.2.2 Two Rank Time-Interleaved Architecture 28
3.2.3 Grouping Technique 30
3.2.3.1 Prior Work 1: The 64-Channel Time-Interleaved 10-Bit SAR ADC [9] 32
3.2.3.2 Prior Work 2: The 4-Channel Time-Interleaved 6-Bit Flash ADC [21] 34
3.2.3.3 Prior Work 3: The 32-Channel Hierarchical Sampling Time-Interleaved 7-Bit SAR ADC [23] 36
3.3 Proposed Time-Interleaved SAR ADC 39
3.3.1 Design Considerations 44
3.3.1.1 Input Bandwidth and Settling Time Requirement 44
3.3.1.2 Offset and Gain Mismatch Calibration 50
3.3.1.3 Timing Skew Mismatch Calibration 51
3.3.1.4 Single-Channel SAR ADC 54
3.3.1.4.1 Asynchronous Processing 54
3.3.1.4.2 Monotonic Capacitor Switching 55
3.3.1.4.3 Dynamic Offset 56
3.3.1.4.4 Arbitrary Weight Capacitor Array (AWCA) Technique 57
3.3.1.4.5 Thermal Noise of AWCA 59
3.4 Summary 59
Chapter 4 Circuit Implementation and Simulation Results 61
4.1 Introduction 61
4.2 Building Blocks and Circuit Implementation 62
4.2.1 Front-End Circuit 62
4.2.2 Bias Circuit 65
4.2.3 Single-Channel SAR ADC 66
4.2.3.1 Sampling Switch 66
4.2.3.2 Arbitrary Weight Capacitor Array (AWCA) 68
4.2.3.3 Comparator 70
4.2.3.4 SAR Logic 72
4.2.3 Clock Generator 75
4.2.4 Delay Line 79
4.2.5 Clock Divider and Multiplexer 80
4.3 Overall ADC Simulation Results 82
4.4 Summary 85
Chapter 5 Measurement Results 86
5.1 Introduction 86
5.2 Floor Plan and Layout Design 86
5.3 PCB Design 89
5.4 Test Setup 94
5.5 Measurement Results 97
5.5.1 Static Performance 97
5.5.2 Dynamic Performance 99
5.6 Discussion 103
5.6.1 Dynamic performance with different RF transformers 103
5.6.2 Analysis of timing skew for simulation and measurement 107
5.7 Summary 113
Chapter 6 Conclusions 115
Chapter 7 Future Work 116
Bibliography 117

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