臺灣博碩士論文加值系統

　　此篇論文提出了兩個實現於台積電0.18-μm互補式金氧半導體製程應用於K頻段之功率放大器，旨在提升電路的線性度、輸出功率、功率附加效率以及退縮功率附加效率的表現。
　　於第一個電路中，我們採用了預失真寄生二極體線性器，功率放大器使用了1.8 V偏壓給電，級間加入了寄生二極體線性器以提高電路整體線性度。此三級共源極之功率放大器在1.8 V以及線性器1.4 V開啟的情況下，實際量測可得K頻段操作的小訊號增益最大值為13.9 dB、OP1dB為14.1 dBm以及15.7 dBm的飽和輸出功率，PAE最大值以及位於OP1dB位置的PAE則分別為14.2%與12.1%，而在P1dB退縮6-dB位置的PAE是為5.2%。再經由雙調測試，可以觀察到此電路出現了一甜蜜點，其在三階互調失真的部分將有18 dBc的消除。
　　在第二個電路中，依據最佳偏壓理論以3 V對功率放大器給電。兩級疊接架構能提供較高增益，也可降低電路匹配複雜度。在加入自動調整偏壓技術後，功率放大器在小訊號操作時將偏壓在AB類操作，大訊號操作時，則自動調整偏壓至A類操作。故可以透過此技術改善在P1dB退縮6-dB位置的PAE、降低電路靜態操作時的直流功耗。根據模擬結果，此功率放大器於K頻段操作的小訊號增益最大值為19 dB、OP1dB為16.9 dBm，位於OP1dB位置的PAE則為11.6%。相較A類操作，自動調整偏壓技術可降低約30%的直流功耗、在P1dB退縮6-dB位置的PAE則可獲得1.1%提升。由實際量測結果，大訊號表現未若模擬結果佳，但自動調整偏壓技術依然能省去14.5%直流功耗。另外為了達到最初的電路規格，我們也嘗試調整最佳化的量測結果。
　　兩個功率放大器中模擬與實際量測的差異因素將會逐一討論，其包括了電磁後模擬的考慮不周、電阻阻值選定、毫米波頻段下的寄生效應以及溫度影響等，我們亦將提供除錯之結果。

In this thesis, two K-band power amplifiers implemented in TSMC 0.18-μm CMOS process are proposed to improve the linearity, output power, PAE and the back-off 6-dB efficiency.
First, a K-band power amplifier using 1.8 V supply voltage utilizing pre-distortion parasitic diode linearizer is designed and measured. Parasitic diode linearizer is utilized to improve overall circuit linearity. With 1.4 V control voltage for the linearizer of 3-stage CS PA turned on, the measured peak small signal gain is 13.9 dB, OP1dB is 14.1 dBm, and saturation power is 15.7 dBm. The PAE has a value of 12.1% at OP1dB, and 5.2% at 6-dB back-off from P1dB. Third-order intermodulation distortion (IMD3) can be mitigated to about 18 dBc when the sweet spot appears under two-tone measurement.
Second, a K-band power amplifier using optimal-selected 3 V supply voltage adopting adaptive-bias technique is designed and measured. The 2-stage cascode PA can provide higher gain and reduce matching complexity. With adaptive-bias circuit, power amplifier can be biasd at class-AB in small signal operation and class-A in large signal operation. Therefore, PAE at 6-dB back-off from P1dB can be improved, and DC power consumption can be reduced. According to the simulation results, this K-band cascade PA provides 19 dB small signal gain, OP1dB is 16.9 dBm, and PAE at OP1dB is 11.6%, PAE at 6-dB back-off from P1dB is 4.6%. Compared with the fixd-bias Class-A PA, the proposed PA saves about 30% power consumption, and the PAE at 6-dB back-off from P1dB can be improved 1.1%. According to the measurement results, large-signal performance is not as good as simulation, but 14.5% DC power consumption can be reduced by the adaptive-bias circuit. In order to meet the specification of this power amplifier, measurement results under optimized condition are provided as well.
The differences between simulation and measurement of both power amplifiers are discussed including factors such as EM post-simulation, resistance selection, parasitic effect and temperature. Finally, debug results are provided.

口試委員會審定書 #
誌謝 i
摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 ix
表目錄 xix
Chapter 1 簡介 1
1.1 背景與動機 1
1.2 文獻研究 2
1.3 頻段選取與偵測生物訊號之連續波雷達簡介 3
1.4 貢獻 6
1.5 論文架構 6
Chapter 2 功率放大器概論 7
2.1 介紹 7
2.2 功率放大器重要參數 8
2.2.1 功率 8
2.2.2 效率 9
2.2.3 線性度 10
2.2.4 功率增益與穩定度理論[19] 14
2.2.5 負載線與負載拉移理論[20] 17
2.2.6 功率放大器分類 22
2.3 線性化技術 26
2.3.1 前饋式(feed-forward)[22] 26
2.3.2 回授式(feedback)[20] 27
2.3.3 預失真(pre-distortion)[23] 28
2.4 功率附加效率提升技術 29
2.4.1 Doherty功率放大器[20] 29
2.4.2 自動調整偏壓技術(adaptive-bias)[9] 30
Chapter 3 採用寄生二極體線性器之功率放大器 31
3.1 Cold-FET線性器介紹 31
3.1.1 線性器操作概念 31
3.1.2 線性器操作原理[23] 32
3.1.3 寄生二極體線性器[24] 35
3.2 已發表相關文獻 36
3.2.1 採用90度延遲線之線性器功率放大器[25][26][27] 36
3.2.2 改動基極偏壓之線性器功率放大器[28] 37
3.2.3 採用寄生二極體之線性器功率放大器[24] 37
3.3 功率放大器設計 38
3.3.1 設計流程 39
3.3.2 輸出級設計尺寸挑選 40
3.3.3 輸出級功率放大器 43
3.3.4 線性器尺寸及偏壓挑選 44
3.3.5 功率分配計算 49
3.3.6 驅動級功率放大器 51
3.3.7 三級共源極功率放大器 53
3.4 模擬結果 54
3.4.1 小訊號模擬 55
3.4.2 穩定度 58
3.4.3 大訊號模擬 60
3.4.4 三階互調失真模擬 63
3.5 量測結果 64
3.5.1 小訊號量測 64
3.5.2 大訊號量測 68
3.5.3 三階互調失真量測 70
3.5.4 修正與討論 71
3.6 總結 83
Chapter 4 採用自動調整偏壓之功率放大器 86
4.1 自動調整偏壓技術介紹 86
4.1.1 自動調整偏壓操作概念 87
4.1.2 自動調整偏壓操作原理[30] 88
4.1.3 各項參數調整及說明[30] 89
4.1.4 自動調整偏壓電路之阻抗[30] 92
4.2 已發表相關文獻 94
4.2.1 採用二極體連接電晶體之自動調整偏壓功率放大器[9] 94
4.2.2 採用場效電晶體型態之可自動調整偏壓功率放大器[29] 95
4.3 電晶體疊接技術 96
4.3.1 共源極及疊接形式比較[31] 96
4.3.2 最佳偏壓選擇理論[32] 97
4.3.3 增益提升技術[6] 103
4.4 功率放大器設計 104
4.4.1 設計流程 105
4.4.2 輸出級設計尺寸挑選 106
4.4.3 輸出級功率放大器 107
4.4.4 輸出級自動調整偏壓電路尺寸及偏壓挑選 108
4.4.5 功率分配計算 109
4.4.6 驅動級功率放大器 109
4.4.7 驅動級自動調整偏壓電路尺寸及偏壓挑選 110
4.4.8 兩級疊接功率放大器 111
4.5 模擬結果 112
4.5.1 小訊號模擬 113
4.5.2 穩定度 117
4.5.3 自動調整偏壓模擬情形 119
4.5.4 大訊號模擬 121
4.6 量測結果 126
4.6.1 小訊號量測 127
4.6.2 大訊號量測 131
4.6.3 自動調整偏壓量測情形 134
4.6.4 三階互調失真量測 137
4.7 修正與討論 138
4.8 總結 164
Chapter 5 結論 168
REFERENCE 169

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