臺灣博碩士論文加值系統

本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器的類比及混合電路設計技術。根據實際的晶片量測結果，我們證實了這些技巧的應用性。
第一個技術是單位電容的布局方法。在不考慮製程變異的情況下，比照之前的設計，我們確保每個單位電容所處在的環境和其他的單位電容是相同的。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其功率消耗為6.2μW，有效位元數為9.47 bits。其品質因數為43.7 fJ/conversion-step。
第二個技術是混合式電容切換程序。我們提出了一個電容切換程序可以減少因電容切換程序而造成在比較器上的動態偏差電壓。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其功率消耗為6.0μW，有效位元數為9.51 bits。其品質因數為41.1 fJ/conversion-step。
這兩個設計都是在0.18μm 1P6M CMOS technology製作的。

This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified.
The first technique is the layout schemes of a unit capacitor. Compared to last work [1], the surroundings of a unit capacitor is identical to each unit capacitor, which does not take process variation into consideration. This relevant prototype SAR ADC consumes 6.2μW at 1-V supply, and the effective number of bit (ENOB) is 9.47 bits. The resultant figure of merit (FoM) is 43.7 fJ/conversion-step.
The second technique is a hybrid capacitor switching procedure. In order to suppress the effect of dynamic offset in the comparator, a capacitor switching procedure is proposed. This relevant prototype SAR ADC consumes 6.0μW at 1-V supply, and the ENOB is 9.51 bits. The resultant FoM is 41.1 fJ/conversion-step.
Both of the prototypes are implemented in a 0.18μm 1P6M CMOS technology.

誌謝 i
中文摘要 iii
ABSTRACT iv
CONTENTS vi
List of Figures x
List of Tables xvi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 The Fundamentals of Analog-to-Digital Converters 3
2.1 Introduction 3
2.2 Performance evaluation parameters 4
2.2.1 Resolution 4
2.2.2 Offset Error and Gain Error 4
2.2.3 Differential Nonlinearity （DNL） 5
2.2.4 Integral Nonlinearity（INL） 6
2.2.5 Signal-to-Noise Ratio（SNR） 7
2.2.6 Signal-to-Noise and Distortion Ratio（SNDR） 7
2.2.7 Effective Number of Bits（ENOB） 7
2.2.8 Total Harmonic Distortion（THD） 8
2.2.9 Spurious Free Dynamic Range（SFDR） 8
2.2.10 Dynamic Range（DR） 9
2.2.11 Figure of Merit（FoM） 10
2.3 ADC Architectures 11
2.3.1 Flash ADC 11
2.3.2 Pipeline ADC 12
2.3.3 Successive Approximation Register ADC 13
2.3.4 Delta-Sigma ADC 14
2.3.5 Comparison of the ADCs 15
Chapter 3 A 1V, 10-bits, Low Power SAR ADC with Shielded-Capacitor Layout Scheme 17
3.1 Introduction 17
3.2 SAR ADC Architecture 18
3.2.1 Basic Operation of Asynchronous SAR ADC 18
3.2.2 The Effect of Parasitic Capacitance in Capacitor Array 25
3.2.3 Digital Error Correction 29
3.2.4 Circuit Implementation 33
3.3 Building Blocks Implementation 36
3.3.1 Sample and Hold Circuit 36
3.3.2 Capacitor Array 44
3.3.3 Dynamic Comparator 48
3.3.4 SAR Control Logic 52
3.3.5 Digital Error Correction Logic 56
3.4 SAR ADC Simulation 58
3.4.1 Function Simulation 58
3.4.2 Dynamic Performance Simulation 59
3.4.3 Static Performance Simulation 62
3.5 Measurement Results 67
3.5.1 The PCB Design 69
3.5.2 Measurement Setup 71
3.5.3 Static Performance Measurement 72
3.5.4 Dynamic Performance Measurement 74
3.5.5 Performance Metric 77
Chapter 4 A 1V, 10-bits, Low Power SAR ADC with Hybrid Capacitor Switching Procedure 78
4.1 Introduction 78
4.2 Power Efficiency Concern in Capacitor Array 79
4.3 Hybrid Capacitor Switching Procedure 80
4.4 SAR ADC Architecture 81
4.4.1 Circuit Implementation 81
4.4.2 SAR ADC Simulation 85
4.4.3 Measurement Results 89
Chapter 5 Conclusions 96
References 97

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