臺灣博碩士論文加值系統

本論文主要為提升OFDM系統傳送接收速率設計基頻硬體電路。在IEEE 802.11 a架構中為了避免訊號處理時產生干擾，故在各級電路中會給予一定的空閒時間，在傅立葉轉換時需要等待五倍封包時間避免干擾。為了提高吞吐量(throughput)，利用深度為五層的指令管線化(instruction pipeline)的傅立葉轉換做為整體架構之基礎。因指令管線化做法可同時處理多個訊號，並可將各級電路中間的空閒時間縮短為零，使系統傳送與接收速度提升為原先的十倍。封包傳輸格式借IEEE 802.11 a做為基礎，搭配IEEE 802.16之載波排列和pilot設計，將傳送頻寬做最更大限度的利用。時序處理是根據Virtex 6基頻電路之最高能承受速度做處理根據IEEE 802.11之原始架構及封包格式做為硬體設計的基礎，基頻設計部分包括封包長度運算、循環冗餘碼(CRC)運算、時序控制(time control)、短訓練符元(short training symbol)、長訓練符元(long training symbol)、系統封包處理(signal frame)等。

The thesis is a design of baseband circuits system to enhance the throughput of OFDM. In IEEE 802.11a protocol, it leaves space between each circuit to avoid signal interference issues, which costs FFT five-times more of the symbol time to process OFDM symbol. In order to enhance the throughput, we use 5 stage of the instruction pipeline as our overall structure of the design. The instruction pipeline of FFT can process multiple signals in the same time. We are able to shorten spare time until it reaches zero. The speed of transmitter and receiver are ten times faster than original speed. The Packet format is based on IEEE 802.11 with the insertion of IEEE 802.16 subcarrier and pilot to maximize bandwidth. Time series is adjusted based upon the highest speed that Virtex 6 baseband circuits are able to endure. Hardware is designed accordingly with the original architect of IEEE 802.11 protocol and packet format. Baseband design contains packet length calculation, cyclic redundancy code calculation, time control, short training symbol, long training symbol, and signal frame.

章節目錄
圖目錄
表目錄
第一章 緒論
第二章 系統架構
2.1 正交分頻多工系統
2.1.1 OFDM Modulation
2.1.2 OFDM的正交性(Orthogonality)
2.1.3 OFDM Demodulation
2.1.4 OFDM調變/解調變的數位化
2.1.5 護衛區間(Guard interval)與循環字首(Cyclic Prefix)
2.2 基頻電路傳送端
2.2.1 Bit Source
2.2.2 Encode & Modulation
2.2.3 Preamble & Output
2.3 基頻電路接收端
2.3.1 Data Input
2.3.2 Carrier Frequency Offset
2.3.3 Preamble & Output
2.3.4 Decode & Frame Check Sequence
第三章 實作平台
3.1 Warp v3 FPGA開發板
3.2 模擬工具與平台
3.2.1 產生Netlist方式
3.2.2 XPS
3.2.3 SDK
3.2.4 MATLAB & Xilinx Tool
3.2.5 Chip Scope
第四章 Time Control
4.1 TX Time Control
4.1.1 Start控制訊號
4.1.2 Modulation控制訊號
4.1.3 IFFT輸出訊號
4.1.4 Output FIFO 控制訊號
4.2 RX Time Control
4.2.1 LTS Correlation控制訊號
4.2.2 Sample Buffer控制訊號
4.2.3 Equalizer控制訊號
4.2.4 FCS Check
第五章 OFDM System
5.1 傳送頻寬
5.1.1 Subcarrier 64 Point Map
5.1.2 Subcarrier 256 Point Map
5.2 IFFT與FFT
5.1.1 Subcarrier 64-Point與256 Point
5.1.2 系統時脈20MHz與160MHz
5.3 IEEE 802.11 無線網路訊框架構
第六章 分析及模擬結果
第七章 結論
附錄：
參考文獻

參考文獻
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