臺灣博碩士論文加值系統

為了追求更好的電性及可靠度，元件閘極材料及結構不斷做改變，鰭式場效電晶體的發展漸取代了傳統平面場效電晶體。本論文中我們對通道長度20nm的N型鰭式場效電晶體進行研究。
鰭式場效電晶體從雙閘極與三閘極的單鰭結構發展到本論文所探討的新型多重鰭結構，我們研究發現多重鰭結構在單一通道下，閘極對通道的控制能力略差於單鰭結構，但因多鰭數增加了等效通道寬度，提升了多重鰭結構整體元件電性。對元件進行熱載子效應測試後，多重鰭結構有較佳元件可靠度，原因在於多重鰭結構通道間有耦合效應的發生。
元件材料從早期的二氧化矽與複晶矽閘極結合轉變成高介電係數材料與金屬閘極的製程，氮化鈦(TiN)及氮化鉭(TaN)為最有可能的金屬材料選擇，我們發現這兩項材料在不同堆疊厚度下會對元件特性產生影響。在TiN/TaN/TiAl閘極金屬堆疊結構中，鉭原子及鋁原子會擴散至高介電係數材料與金屬閘極之間形成偶極子，改變有效功函數，影響臨界電壓。當閘極阻隔層(TiN/TaN)厚度越厚，越能防止鋁原子擴散至介面層，以阻止功函數往中能隙偏移。
進一步對不同金屬閘極厚度的元件做熱載子實驗，發現鉭原子擴散與二氧化鉿形成的氧化鉿鉭(Hf-Ta-O)可使矽-氧介面較完整，提升可靠度。而鋁原子擴散與二氧化鉿形成的氧化鉿鋁(Hf-Al-O)則會造成電性壓迫後臨界電壓偏移量增加。對元件施加不同電壓的熱載子實驗，亦得到氮化鉭層堆疊厚度較厚結構擁有較佳元件可靠度及穩定度。

In order to achieve better electrical characteristics and reliability, device material and structure are contineously improved. Progressively, traditional planar MOSFET has been replaced by FinFET devices. In this work, N-type FinFETs with 20nm channel length are investigated.
FinFET developed from double gate to tri-gate single-fin structure, followed by multi-fin structure, which is investigated in this work. It is found that multi-fin structure provides better device performance than single-fin structure due to increased effective gate width, although the capability to control the gate is weaker under each fin for multi-fin structure. Furthermore, multi-fin structure shows better reliability under hot carrier injection (HCI) stress, which may be attributed to the existing of coupling effects between neighboring fins in multi-fin structure.
Gate material has transformed from traditional SiO2/poly-Si gate to high-k/metal gate (HK/MG). TiN and TaN are two of the most potential candidates for metal gate. It is found that TiN and TaN with different stack thickness can affect device characteristics. For TiN/TaN/TiAl metal gate stack, Ta and Al atoms will diffuse to the interface between metal gate and high-k layer to form dipoles, which can change the effective work function (EWF) and threshold voltage (VTH). When the barrier layer TiN/TaN becomes thicker, the Al diffusion to interface and EWF shift to mid-gap can be prevented.
Moreover, devices with different gate stack thickness have been characterized under HCI stress. It is suggested that Ta atoms diffuse into HfO2 to form Hf-Ta-O, which results in high-quality Si-O interface and impoves reliability. While the diffusion of Al atoms easily form Hf-Al-O, which induces more VTH shift after HCI stress. Different HCI stress voltages were further performed and the conclusion is similar that devices with thicker TaN stack show better reliability and stability.

摘要
Abstract
誌謝
目錄
圖目錄
第一章 緒論
1.1 研究背景與動機
1.2 文獻探討
1.3 論文架構
第二章 元件基本量測與結果分析
2.1 FinFET元件製程
2.1.1 實驗儀器之簡介
2.1.2 量測數據之處理
2.2 量測方法與實驗步驟
2.3 元件基本電性量測之實驗設計
2.3.1 ID-VG特性曲線
2.3.2 IG-VG特性曲線
2.3.3 ID-VD特性曲線
2.4 基本電性量測參數分析
2.4.1 臨界電壓(VTH)
2.4.2 轉移電導(GM)
2.4.4 飽和電流(ID,sat)
2.5 元件可靠度量測理論
2.5.1 熱載子效應(Hot Carrier Effect)
第三章 不同鰭數目之元件基本電性分析與可靠度研究
3.1 不同鰭數目之元件基本電性分析
3.1.1 不同鰭數目基本電性量測實驗設計
3.1.2 不同鰭數目之元件電性分析
3.2 不同鰭數目之元件可靠度研究
3.2.1 熱載子效應實驗設計
3.2.2 熱載子效應實驗結果分析
第四章 不同金屬閘極材料結構之元件基本電性分析與可靠度研究
4.1 不同金屬閘極材料結構之元件基本電性分析
4.1.1 不同金屬閘極材料結構基本電性量測實驗設計
4.1.2 不同金屬閘極材料結構之元件電性分析
4.2 不同金屬閘極材料結構之元件可靠度研究
4.2.1 熱載子效應實驗設計
4.2.2 熱載子效應實驗結果分析
第五章 結論與未來展望
5.1 結論
5.2 未來展望
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