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[1]2015, The International Technology Roadmap for Semiconductor, ITRS. [2]S. P. Murarka, Multilevel interconnections for ULSI and GSI era, Mater. Sci. Eng., R, 19(1997) 87–151. [3]L. Peters, Advancing aluminum interconnect technology, Semiconductor International,(1998) 83. [4]S. P. Murarka, R.J. Gutmann, Advanced multilayer metallization schemes with copper as interconnection metal, Thin Solid Films, 236(1993) 257-266. [5]T. Licata,J. Gambino, S. Nguyen, M. Ronay,Dual Damascene A1 wiring for 256M DRAM,VMIC,91 (1995) 596. [6]R.F. Schnabl, D. Dobuzinsky, J. Gambino, K.P. Muller, F. Wang, D.C. Perng, H. Palm,Dry etch challenges of 0.25 μm dual damascene structures, Microelectron. Eng.,37-38(1997) 59-65. [7]Peter Singer, Semiconductor International, (1997) 79. [8]M. R. Baklanov, S. Vanhaelemeersch, H. Bender, K. Maex,Effects of oxygen and fluorine on the dry etch characteristics of organic low-k dielectrics, Vac. Sci. Technol., 17(1999) 372. [9]Laura Peters, Semiconductor International, (1998) 64. [10] O. Chyan, T. N. Arunagiri, T. Ponnuswamy, Electrodeposition of Copper Thin Film on Ruthenium. A Potential Diffusion Barrier for Cu Interconnects,J. Electrochem. Soc., 150 (2003) 347-350. [11] D. Josell, D. Wheeler, C. Witt, T. P. Moffat, Seedless Superfill: Copper Electrodeposition in Trenches with Ruthenium Barriers, Electrochem.
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