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研究生:陳建翰
研究生(外文):Jian-Han Chen
論文名稱:使用適應性導通時間控制與鎖相鎖頻技術之快速動態電壓調節電流式降壓轉換器
論文名稱(外文):A Fast-Dynamic-Voltage-Regulation Current-Mode Buck Converter with Adaptive On-Time Controlled and Phase-Frequency-Locked Techniques
指導教授:黃育賢陳建中陳建中引用關係
指導教授(外文):Yuh-Shyan HwangJiann-Jong Chen
口試委員:郭建宏宋國明黃育賢陳建中
口試委員(外文):Chien-Hung KuoGuo-Ming SungYuh-Shyan HwangJiann-Jong Chen
口試日期:2016-07-26
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電子工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:104
語文別:中文
中文關鍵詞:降壓式轉換器、固定導通時間控制、鎖相鎖頻技術、適應性導通時間控制、快暫態響應
外文關鍵詞:Buck converterconstant on-timephase-frequency-lockedadaptive on-timefast-transient response
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  • 被引用被引用:2
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本論文分兩部分,第一部分為使用適應性導通時間控制之快速動態電壓調節電流式降壓轉換器,此控制電路分為兩個迴路路徑,一個為主要電流回授路徑,另一個為動態加速電路,藉由包含感測電流變化故更能加快暫態反應時間,最後藉由自適應性導通時間產生器來自動調節適合的切換頻率。電路使用台灣積體電路公司0.35-um互補式金屬氧化物半導體製程來實現,電源晶片面積1.3277 x 1.3508 mm2,操作電壓為3V到3.6V,輸出電壓為1.8V,在負載電流為120mA時,最高效率為92.5%。
  論文第二部分,基於第一部分的電路架構做改善,在第一部分的系統中並沒有回授校正,容易受到非理想效應而有所偏差,故提出了使用鎖相鎖頻技術來達到鎖頻效果,解決適應性導通時間控制切換頻率不固定的缺點,並維持第一部分快速響應。電路使用台灣積體電路公司0.35-um互補式金屬氧化物半導體製程來實現,電源晶片面積為1.450 x 1.405 mm2,操作電壓為3V到3.6V,輸出電壓為1.8V,在負載電流為130mA時,最高效率為95.05%。 
The major research of this thesis can be divided into two parts. The first part proposes a fast-dynamic voltage regulation current mode buck converter with adaptive on-time controlled techniques. The control block of the circuit can be divided into two feedback loops. One is the current feedback path, and the other is the fast-dynamic feedback path. The current sensing circuit accelerates the transient response of the circuit, and the adaptive constant on time generator self-adjusts the switching frequency. The circuit is implemented with TSMC 0.35um DPQM CMOS process, and the chip area is 1.3277 × 1.3508 mm2. The input voltage range is 3~3.6 V and the output voltage is 1.8 V. When the output current is 120 mA, the circuit has the highest efficiency of 92.5%.
The second part of this thesis proposes a fast-dynamic-voltage-regulation current-mode buck converter with adaptive on-time controlled and phase-frequency-locked techniques, which solve the defect of the first proposed circuit and maintain the advantage of that circuit. Because the first proposed circuit does not have feedback correction mechanism, its switching frequency is easily affected by non-ideal effects. Therefore, the second part proposes a phase-frequency-locked technique to lock the switching frequency, but it still maintains the advantages of the first proposed circuit, the fast transient response. The circuit is implemented with a TSMC 0.35um DPQM CMOS process, and the chip area is 1.450 x 1.405 mm2. The input voltage range is 3~3.6 V and the output voltage is 1.8 V. When the output current is 130 mA, the circuit has the highest efficiency of 95.05%.
摘要 i
ABSTRACT ii
誌謝 iv
目錄 v
表目錄 viii
圖目錄 ix
第一章 序論 1
1.1相關研究發展近況 1
1.2研究動機與目的 4
1.3論文架構 5
第二章 切換式降壓轉換器動作原理分析 6
2.1 切換式降壓轉換器原理 6
2.1.1連續導通模式 8
2.1.2非連續導通模式 12
2.1.3邊界導通模式 14
2.2切換式轉換器之電流控制技術 15
2.2.1脈波寬度調變 15
2.2.2遲滯控制 16
2.2.3固定導通時間控制 16
2.3切換式直流-直流轉換器特性與定義 18
2.3.1輸出電壓漣波 18
2.3.2線性調節 18
2.3.3負載調節 19
2.3.4暫態響應 19
2.3.5效率 20
第三章 使用適應性導通時間控制之快速動態電壓調節電流式降壓轉換器 22
3.1設計目標 22
3.2架構簡介 23
3.2.1運算放大器 24
3.2.3主動式電流感測電路 25
3.2.4取樣與保持電路 27
3.2.5動態加速電路 28
3.2.6適應性導通時間控制器 28
3.2.7非重疊電路與驅動電路 30
3.3電路模擬 31
3.3.1 PSIM行為模擬 31
3.3.2 Hspice 模擬 34
3.4整體電路佈局與量測結果 37
3.4.1晶片佈局 37
3.4.2晶片腳位與定義 38
3.4.3量測環境 40
3.4.4量測結果 41
3.3.5規格表與相關文獻比較 44
第四章 使用適應性導通時間控制與鎖相鎖頻技術之快速動態電壓調節電流式降壓轉換器 46
4.1架構簡介 46
4.1.1適應性導通時間控制器 47
4.1.2相位頻率檢測器電路 48
4.1.3電荷幫浦 48
4.1.4低通濾波器 49
4.2電路特性模擬 52
4.3整體電路佈局與量測結果 57
4.3.1晶片佈局 57
4.3.2晶片腳位與定義 58
4.3.3量測環境 60
4.3.5規格表與相關文獻比較 61
第五章 結論與未來展望 63
5.1結論 63
5.2未來展望 64
參考文獻 65
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