臺灣博碩士論文加值系統

本論文旨在設計一種切換電流式的十位元管線型類比數位轉換器，其架構共計九級，前面八級為1.5位元的架構，最後一級為兩位元架構，據此完成十位元的管線型架構。此外，本論文也利用數位校正電路來校正比較器所造成的誤差，並在切換電流式的架構下，利用主動回授式電流鏡來降低輸入阻抗與改善通道長度調變效應，以及使用虛開關來減少通道電荷注入和時脈潰入的誤差，藉此得到信號匹配的精確度及改善傳遞誤差。
本論文提出一個取樣率可達到每秒200MHz、解析度10位元的管線型類比數位轉換器，其主電路採用電流模式。以電流模式的數位類比轉換器為例，該轉換器係透過電流訊號的輸出點直接並聯，完成電流訊號的加減法；不同於切換電容式的數位類比轉換器，電流切換式的數位類比轉換器在佈局面積、速度與解析度上皆有較佳的效能。
本論文設計係採用TSMC 0.18μm 1P6M標準製程，其模擬結果顯示(R+C)，在輸入頻率為5MHz的弦波訊號及取樣率為每秒200MHz的條件下進行模擬，其最大的訊號雜訊失真比(SNDR)可達到61.07dB，相當於有效位元數(ENOB)約9.85位元；晶片在1.8V的供應電壓下，消耗功率約為56毫瓦特，電路的單端工作電流範圍為-20µA~+20µA，FOM值可達0.3pJ/conversion，核心晶片面積約為1.2×1.2 mm2。

The thesis presents a switched-current pipelined analog-to-digital converter(ADC) which consists of 8 stages in 1.5-bit/stage, and one stage in 2-bit/stage. Notify that a digital error correction circuit is used to correct the offset error of comparator in the pipelined ADC. Furthermore, not only the active feedback is used to decrease the input impedance and reduce the channel-length modulation effect, but also the dummy switch is adopted to decrease the signal-dependent charge-injection and clock feedthrough error. Those adopted techniques can decrease the transmission error effectively.
This study presents a pipelined ADC, including a sampling rate of 200Ms/s and a resolution of 10 bits. Notify that the whole structure is completed with the switched-current mode. In the current mode, two operation of ADC, addition and subtraction, are implemented by connecting the current signals in parallel. Comparing to the switched-capacitance DAC, the switched-current DAC performs with many merits, such as small chip area, high speed and good resolution.
Post-layout simulations show that the signal-to-noise and distortion ratio(SNDR) is 61.07dB whose effective number of bit (ENOB) is 9.85 bits at the input frequency of 5MHz and the sampling rate of 200Ms/s. The power consumption is about 56 mw at the supply voltage of 1.8 V. Notify that the figure of merit is roughly 0.3 pJ/conversion the current range is from -20µA to +20µA, and the chip area is roughly 1.2×1.2〖mm〗^2.

摘 要 i
Abstract iii
誌謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章 高速類比數位轉換器架構 4
2.1 類比數位轉換器效能參數 4
2.1.1 動態特性參數 4
2.1.2 靜態特性參數 10
2.2 快閃式(Flash)類比數位轉換器電路架構 14
2.3 兩階式(Two-Step)類比數位轉換器電路架構 16
2.4 管線式(Pipelined)類比數位轉換器之架構原理 17
第三章 1.5-bit/stage 管線式類比數位轉換器 21
3.1 設計原理 21
3.2 電流模式之架構與演算方法 26
第四章 電路設計與模擬 31
4.1 切換電流技術 31
4.2 電流鏡設計考量 41
4.3 類比電路之設計及模擬結果 46
4.3.1 取樣保持電路 46
4.3.2 低輸入阻抗電流比較器 49
4.3.3 1.5位元之子類比數位轉換器 51
4.3.4 2位元之子類比數位轉換器 59
4.3.5 數位類比轉換器電路 60
4.4 數位電路之設計及模擬結果 62
4.4.1 暫存器電路 62
4.4.2 數位錯誤更正電路 63
4.4.3 非重疊時脈產生器 65
4.5 整體電路結果 66
4.6 效能總結與規格比較 70
第五章 系統佈局與量測 72
5.1 佈局考量 72
5.1.1簡介 72
5.1.2 類比電路佈局考量 73
5.1.3 訊號線佈線規劃 74
5.1.4 電源線佈線規劃 76
5.1.5 系統電路佈局與佈局後模擬 77
5.2 量測環境 82
5.3 量測結果 83
第六章 結論與未來研究方向 92
6.1 結論 92
6.2 未來研究方向 93
參考文獻 94

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