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研究生:白承偉
研究生(外文):Cheng-Wei Bai
論文名稱:熱載子加壓下28 nm HK/MG NMOSFETs的基底電流特性
論文名稱(外文):Substrate Current Characteristics for 28 nm HK/MG NMOSFETs under Hot Carrier Stress
指導教授:黃恆盛;王木俊
指導教授(外文):Heng-Sheng Huang;Mu-Chung Wang
口試委員:黃恆盛;王木俊;陳雙源;王錫九
口試委員(外文):Heng-Sheng Huang;Mu-Chung Wang;Shuang-Yuan CHEN;Shea-Jue Wang ; Win-Der Lee
口試日期:20160715
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:104
語文別:中文
中文關鍵詞:熱載子效應、撞擊游離、基底電流、汲極電流、生命週期
外文關鍵詞:Hot carrierImpact ionizationSubstrate currentDrain currentLifetime
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早期文獻指出次微米製程下基底電流(ISUB)為監測熱載子效應的方法,因此基底電流(ISUB)為nMOSFET元件可靠度的重要參考因素。但鮮少有文獻探討奈米等級nMOSFET,基底電流於不同通道長度下及熱載子加壓後的變化,所以本論文以此為研究方向。
本研究用聯華電子所提供的28nm nMOSFET。其閘極層是利用原子層沉積技術(ALD)製作,選用氧化鋯鉿(HfZrOx)的高介電材料。研究中量測不同通道長度nMOSFET的ISUB,測試方法為閘極偏壓-0.4 V~2.3 V,汲極定電壓 2.3 V,研究結果顯示長通道元件的ISUB與短通道元件的ISUB相比,在比較小的VG/VD發生最大值,是由於短通道元件有較大的導通電流(IDS)去碰撞出較多的電子電洞對,需要更多的反轉層電荷去覆合掉電洞,而在熱載子加壓方面,通道熱載子加壓條件為VG=VD=1.2 V、1.4 V、1.6 V,汲極雪崩熱載子加壓條件為VG=ISUBMAX, VD=1.2 V、1.4 V、1.6 V,測試後基底電流(ISUB)變小,是由於加壓後的汲極電流(IDS)變小,使的碰撞出來的電子電洞對變少所導致,而臨界電壓偏移和基本電性劣化方面,短通道元件比長通道元件偏移嚴重,是因為短通道元件有比較大的導通電流和水平電場,造成加壓後界面能態及氧化層陷入電荷大幅上升,通道熱載子(CHC)加壓又比汲極雪崩熱載子(DAHC)加壓偏移嚴重,是由於通道熱載子加壓有比較大的閘極電壓。
元件生命週期預測採用τ*ID / W – ISUB / ID模型來計算生命週期參數m,計算後的m值的大小為1.1,和早期的m值(2.9 ~ 3.3)相比變小,代表要造成介面能態就更容易。本研究針對基底電流(ISUB)行為做了更進一步的研究,比較CHC和DAHC的元件劣化程度,且用早期的生命週期模型計算元件生命週期參數m,應深具參考價值。未來之研究可探討不同溫度,pMOSFET或是不同製程方式的元件。
The hot carrier effect is usually monitored by the substrate current in submicrometer process. The substrate current is an important issue. Due to only a few recent researchers in-vestigating the substrate current of nano-node nMOSFETs under the hot carrier stress, there-fore, the main study in this thesis focuses on this trend.
In this work, the tested 28nm wafers came from UMC. The hafnium-based gate dielec-tric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited with atomic layer deposition (ALD) technology. We measure substrate current (ISUB) with different channel lengths. The test conditions set gate bias from -0.4 V to 2.3 V and set drain bias at 2.3 V. The results show that when ISUB reaches maximum, the VG/VD value in long channel length is smaller than short channel length. It’s due to on current (IDS), short channel devices has bigger IDS to impact more hole pairs which need higher VG to generate more inversion charges let substrate current decline. It’s more difficult to recombinant holes let substrate decline. The hot carrier (HC) stress, the channel hot carrier stress condition is VG=VD=1.2 V, 1.4 V, 1.6 V, the drain ava-lanche hot carrier stress condition is VG=ISUBMAX, VD=1.2 V, 1.4 V, 1.6 V. After HC stress, the ISUB become smaller because IDS is smaller than the initial IDS, the smaller IDS cause hole pairs become less. The threshold voltage (VT) shift and electrical characteristic degradation in short channel devices are more serious than long channel devices, because short channel devices have bigger IDS and horizontal field, let the interface state and oxide trap in short channel in-crease more serious after stress. The VT shift of channel hot carrier (CHC) stress is more seri-ous than the drain avalanche hot carrier (DAHC) because CHC stress mode has bigger gate voltage.
The device lifetime use the τ*ID / W – ISUB / ID model for calculating lifetime parameter m, the former research have been reported the m ranging between 2.9 ~ 3.3, the lifetime pa-rameter m in our research is about 1.1. It means that the critical energy of interface states be-come smaller and easier to generate interface state.
This research have the value of reference to research substrate current deeper, compare CHC degradation with DAHC degradation and use former lifetime model to calculate device lifetime. In the future, this research can be extended to probe the relationship such as different temperature, pMOSFET and different process devices.
摘要 i
誌 謝 v
ABSTRACT iii
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xv
Chapter 1 INTRODUCTION 1
1.1 Background 1
1.2 Thesis Organization 2
Chapter 2 BASIC PROPERTY OF STACKED HIGH-k/METAL GATE MOSFETS AND DEVICE RELIABILITY 3
2.1 Shrinking Trend of the MOSFETs 3
2.2 Silicon Dioxide to High-k/Metal Gate Dielectric 4
2.3 Research about High-k/Metal Gate Dielectric 9
2.3.1 Introduction of hafnium zirconate gate dielectric 9
2.3.2 ZrO2 position effect of ALD HfZrOx gate dielectric 11
2.3.3 The high density of defects in Hf-based dielectrics 13
2.4 Research about Hot-Carrier Effect of High-k Dielectrics 15
2.4.1 Introduction of hot-carrier effect (HCE) 15
2.4.2 Physical mechanism for hot-carrier effect 16
2.4.2.1 Channel hot-carrier (CHC) stress 16
2.4.2.2 Drain avalanche hot-carrier (DAHC) stress 16
2.4.3 The worst case issue under HC 19
2.5 Gate-Induced Drain Leakage (GIDL) 24
2.5.1 GIDL current mechanism 24
2.5.2 The relationship between GIDL current and bulk traps 25
2.6 Problem Formation 26
Chapter 3 EXPERIMENTALS 27
3.1 The Structure of Devices 27
3.2 Experimental Profiles 28
3.3 Measurement and Stress Conditions 29
Chapter 4 RESULTS AND DISCUSSION 31
4.1 Discussion of The Characteristics of nMOSFETs with Different Channel Lengths 31
4.1.1 The ID-VD characteristic curves for nMOSFETs 31
4.1.2 The ID,lin –VG curves for nMOSFETs 33
4.1.3 Trans-conductance characteristics degradation for nMOSFETs 35
4.2 Discussion of the Substrate Current Characteristics of nMOSFETs with Different Channel Lengths 37
4.2.1 Impact ionization rate in nMOSFETs 43
4.2.2 The short channel nMOSFETs substrate current decline 43
4.3 Substrate Current Maximum Shift 45
4.4 HC Stress for Different Channel Length Conditions of nMOSFETs 47
4.4.1 Substrate current degradation after CHC stress. 47
4.4.2 VT shift after CHC stress. 52
4.4.3 Substrate current degradation after DAHC stress. 57
4.4.4 VT shift after DAHC stress. 60
4.4.5 Comparison of VT shift after CHC and DAHC stress. 63
4.5 CHC Stress Lifetime Model of nMOSFETs 65
Chapter 5 CONCLUSION AND FUTURE WORKS 67
5.1 Conclusions 67
5.2 Future Works 68
REFERENCES 69
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