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研究生:蔡佳佑
研究生(外文):Chia-Yu Tsai
論文名稱:28 nm節點nMOSFETs之寫入方式
論文名稱(外文):Programming methods for 28 nm node nMOSFETs
指導教授:王錫九黃恆盛黃恆盛引用關係
口試委員:李文德陳雙源王木俊王錫九黃恆盛
口試日期:2016-07-13
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
畢業學年度:104
語文別:英文
中文關鍵詞:原子層沉積、氧化鋯鉿、快閃記憶體、非揮發性記憶體、通道熱載子注入
外文關鍵詞:Atomic Layer Deposition (ALD)HfxZryOzFlash memoryNonvolatile memoryChannel Hot Carrier injection
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隨著半導體製程技術的迅速發展,快閃記憶體 (flash memory)元件已被廣泛的應用成為主要的非揮發性記憶體(nonvolatile memory)。在本論文中利用傳統邏輯製程的MOSFETs進行寫入,若是能夠有效的將一般的nMOSFET當作記憶體來使用,不用另外開一道使用記憶體的製程,可以節省巨幅製程成本,也可使面積縮小許多,為一整合製程的重要關鍵。
本研究是使用聯華電子所提供的28 nm製程nMOSFET,閘極介電層是利用原子層沉積技術(Atomic Layer Deposition, ALD),製作氧化鋯鉿(HfxZryOz)。為找到其寫入條件,論文主要研究兩種寫入方式,第一種方式通道熱載子注入,發現在L=0.035um的元件上VT變化量較大且時間較快,但會有誤寫入之問題,這對於記憶體元件來說,在進行多次的寫入與抹除上會有很大的挑戰,且在L=0.035um以上的元件較不容易寫入;第二種方式為本研究所提出新的寫入方式,雖然VT的變化量較小時間慢,但不會有誤寫入的問題。最後針對這兩種寫入方式做改善,將適用L=0.035 um的元件來測試,發現利用汲極雪崩熱載子注入方式可使漏電流變小、且誤寫入較不嚴重。在未來可再繼續研究將其nMOSFET抹除的方式及可靠性,元件在寫入之後,電子是否能夠保持很長的一段時間而不會流失,為接下來探討的重點。
Recently, Semiconductor device process technology has developed the rapidly on flash memory technology. This research uses conventional logic MOSFETs to programming. If it can efficiently program in logic device, no need to build specialist system of memory process. It can cost less and reduces the area. It’s the key point of process integration.
In this work, the tested 28 nm sample wafers came from UMC. The hafnium-based gate dielectric with a profile of HfO2/ZrO2/HfO2 was deposited with atomic layer deposition (ALD) technology. To find the programing condition, we study two methods. First one is Channel Hot Carrier Injection (CHCI). Its VT variety is bigger and more efficiency. But it has a problem in disturb. It’s a challenge for memory device to P/E repeatedly. The devices which are beyond L=0.035um are more difficult to program. The second method is posed in our research, let the VT of all device reach VCC without disturb problem, but waste more programming time than CHCI. Finally we modify these two methods in length 0.035um. Find that Drain Avalanche Hot Carrier Injection (DAHCI) can reduce the leakage current and the disturbed problem. In the future, we can study its erase behavior and device reliability. Electric can retain in oxide for a long time after programming or not. Its the main work for the future.
CONTENTS
摘 要 i
ABSTRACT iii
致 謝 v
LIST OF TABLES ix
LIST OF FIGURES x
Chapter 1 INTRODUCTION 1
1.1 Preview 1
1.2 Thesis Organization 2
Chapter 2 3
HIGH-K GATE DIELECTRICS AND STACKED-GATE FLASH MEMORY DEVICES 3
2.1 Trend of Device Shrinking 3
2.2 The Replacement of SiO2 3
2.3 Introduction of Flash Memory 6
2.3.1 Flash Memory Structure and Capacitance Model 9
2.4 Carrier Transport Classification 11
2.4.1 Channel Hot Electron Injection 12
2.4.2 Drain Avalanche Hot Carrier Injection 13
2.4.3 Fowler-Nordheim Tunneling 14
2.4.4 Comparisons of Programming Operations 15
2.5 Array Architecture 16
2.5.1 NOR-type Flash Memory 16
2.5.2 NAND-type Flash Memory 17
Chapter 3 EXPERIMENTAL DESIGNS 19
3.1 Experimental Procedures 19
3.2 Experimental Structure Process 20
3.3 Measurement Conditions 22
Chapter 4 RESULTS AND DICUSSION 24
4.1 The Research of CHCI 24
4.1.1 ID-VG Characteristics of CHCI 24
4.1.2 Program Characteristics of nMOSFET 26
4.1.3 The Comparison of Leakage Current with Initial Condition and after Stress/Program 28
4.2 The Research of Gate Open Programming 30
4.2.1 ID-VG Characteristics of Gate Open 30
4.2.2 Program Characteristics of nMOSFET 32
4.2.3 The Comparison of Leakage Current with Initial Condition and after Stress/Program 33
4.2.4 Coupling Voltage for Gate Open 35
4.2.5 How to Find Erase Condition 37
4.3 Summary of Two Methods 39
4.3.1 Compare with the Program Characteristics of nMOSFET 39
4.3.2 The Comparison of Two Programming Methods Leakage Current with Initial Condition and after Stress/Programming 40
4.3.3 Compare with the Matrix Organization 42
4.4 The Research of DAHCI 44
4.4.1 ID-VG Characteristics of DAHCI 44
4.4.2 Program Characteristics of nMOSFET 45
4.4.3 The Comparison of Leakage Current with Initial Condition and after Stress/Programming 46
4.4.4 Compare with the Matrix Organization 47
Chapter 5 48
CONCLUSION AND FUTURE WORKS 48
5.1 Conclusion 48
5.2 Future Works 48
REFERENCES 50
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