臺灣博碩士論文加值系統

本論文提出混合式三項浮點加法器的改良架構，混合式三項浮點加法器是將兩個兩項浮點加法器結合成單一元件，達到比傳統漣波加法器架構更好的效能表現與更精準的精確度。為了讓混合式三項浮點加法器達到更好的效益，我們提出四個優化技術，如下：改良設計指數比較與有效數對齊、1補數表示法、前導零預測與檢測和提早正規化等。
本論文所提出的設計，以Verilog硬體描述語言進行暫存器轉移層（RTL）邏輯的驗證，然後是用Synopsys 的Design Compiler在TSMC 0.13 μm標準元件庫下合成，合成後在考慮元件延遲的條件下本論文架構的延遲時間為10.23 ns，電路面積為94725 μm2 ，與近年所提出文獻[1]的優化混合式三項浮點加法器架構比較，延遲時間為相同，而面積減少了33%，達到本論文的低成本之目的。

This thesis presents improved architecture for a fused floating-point three-term adder. The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a cascade of traditional floating-point two-term adders, which is referred to as a discrete design. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, one’s complement representation, leading zero anticipation and early normalization.
The proposed design is implemented by Verilog hardware description language in the register transfer level (RTL) , and synthesized with a 0.13μm TSMC standard-cell library by Design Compiler. After synthesis, the latency of the circuit is 10.23ns and the core area is 94725μm2. The improved low cost fuse floating-point three-term adder reduces the area by about 33% compared to the architecture proposed in [1] at the same latency.

摘要
ABSTRACT
誌謝
目錄
圖目錄
表目錄
第一章 緒論
1.1 研究動機
1.2 研究方向
1.3 論文大綱
第二章 研究背景
2.1 IEEE-754二進位浮點數算術標準
2.1.1 浮點數格式
2.1.2 浮點數之加減法
2.2 加法器
2.2.1 漣波進位加法器
2.2.2 前瞻進位加法器
2.2.3 進位選擇加法器
2.3 並行前綴加法器
2.3.1 Ladner-Fischer加法器
2.3.2 Kogge-Stone加法器
2.3.3 Brent-Kung加法器
2.3.4 Han-Carlson加法器
2.4 前導零預測與檢測
第三章 混合式三項浮點加法器架構
3.1 特殊設計指數比較與有效數對齊
3.2 雙反向縮項運算
3.3 三項輸入LZA/LZD
3.4 提早正規化
3.5 複合加法與捨入設計
第四章 低成本混合式三項浮點加法器架構與實現
4.1 架構
4.2 指數比較與有效數對齊
4.3 加法前置架構與提早正規化
4.3.1 1補數表示法
4.3.2 反向器控制
4.3.3 進位儲存加法器
4.3.4 局部前瞻進位加法器
4.3.5 LZA/LZD
4.3.6 提早正規化
4.4 加法與捨入
4.5 指數校正
4.6 符號校正
第五章 實驗結果
5.1 實驗步驟與方法
5.2 數據比較
第六章 結論與未來方向
6.1 結論
6.2 未來方向
參考文獻

[1] J. Sohn and E. E. Swartzlander, "A Fused Floating-Point Three-Term Adder," IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2842-2850, Oct 2014.
[2] "IEEE Standard for Floating-Point Arithmetic," ANSI/IEEE Standard 754-2008, IEEE, 2008.
[3] "Hardware Algorithms for Arithmetic Modules," Aug 2007. [Online]. Available: http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_rcl.
[4] R.E. Ladner and M.J. Fischer, "Parallel Prefix Computation," Journal of the Assoaatton for Computing Mactnnery, vol. 27, no. 4, pp. 831-838, Oct 1980.
[5] P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Transactions on Computers, pp. 786-793, 1973.
[6] M. S. Schmookler and K. J. Nowka, "Leading Zero Anticipation and Detection - A Comparison of Methods," Proc. 15th IEEE Symp. Computer Arithmetic, pp. 7-12, 2001.
[7] M. S. Schmookler and D. G. M. Jr., "Two State Leading Zero/One Anticipator (LZA)". United States Patent 5,493,520, Feb 1996.
[8] T. Yao, D. Gao, X. Fan and X. Ren, "Three-Operand Floating-Point Adder," IEEE 12th International Conference on Computer and Information Technology, pp. 192-196, 2012.
[9] K. T. Lee and K. J. Nowka, "1 GHz Leading Zero Anticipator Using Independent Sign-bit Determination Logic," VLSI Circuits Digest of Technical Papers, pp. 194-195, 2000.
[10] T. Lang and J. D. Bruguera, "Floating-Point Multiply-Add-Fused with Reduced Latency," IEEE Transactions on Computers , pp. 988-1003, 2004.
[11] Synopsys, "DesignWare Building Block IP Documentation Overview," 2012.
[12] "TSMC 0.13 µm (CL013G) Process 1.2-Volt SAGE-X TM Standard Cell Library Databook," 2004.