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研究生:鄭明仁
研究生(外文):CHENG, MING-JEN
論文名稱:改良型微小化、雙頻兼具諧波抑制180゚分合波器之設計研究
論文名稱(外文):Design and study of improved Miniature and Dual-Band 180˚ Hybrid Coupler with Harmonic-Suppression
指導教授:陳志強陳志強引用關係
指導教授(外文):CHEN, CHIH-CHIANG
口試委員:沈昭元曾振東
口試委員(外文):SIM, CHOW-YEN-DESMONDTSENG, JAN-DONG
口試日期:2017-07-05
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:130
中文關鍵詞:180゚分合波器微小化雙頻諧波抑制互補傳導線帶步階式阻抗諧振器雙層開路殘段
外文關鍵詞:180˚ hybrid couplerminiaturizeddual-bandharmonic-suppressioncomplementary-conducting-stripstepped impedance resonatortwo-layers open stub
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本論文針對180˚分合波器進行設計、改良,使其成為具有小型化兼具諧波抑制及雙頻功能之電路。運用步階阻抗輔以互補傳導線帶(complementary-conducting-strip, CCS)傳輸線進行設計,形成之單元模組為基礎架構取代全長為6/4-λg傳統分合波器中每一個1/4-λg傳輸線段,適當的比例設計使電路小型化並兼具雙頻功能,再加上雙層開路殘段來進行諧波抑制。
使用CCS TL取代傳統微帶線,透過萃取在不同規格下之CCS TL電氣參數,來構成步階阻抗線段以及開路殘段,並以此單元模組來取代傳統環形(ring-shape)微帶180˚分合波器中的1/4-λg傳輸線段。將六個單元模組串連形成全長為6/4-λg之雙頻(2.45/5.8-GHz)兼具諧波抑制且微小化的180˚分合波器。
研究結果顯示:所提出此種新型180˚分合波器之正六邊形電路佔用面積 (不含I/O PADs) (=1.5√3  a2,其邊長 a 為7.3 mm)僅為138.41 mm2,為傳統環形180˚分合波器佔用面積(不含I/O PADs)(= π × b2,其半徑b為18.44 mm)的13 %,面積縮裝率(area reduction factor, ARF)高達87 %。
從研製180˚分合波器之原型電路的電氣量測結果,實作較模擬結果往高頻偏移0.1 GHz,最佳的頻率點從(f1/f2,2.45/5.8-GHz)移至(f1’/f2’,2.55/5.9-GHz)。透過實作顯示出該電路具有雙頻操作(f1’/f2’,2.55/5.9-GHz)及諧波抑制的特性。有關雙頻操作電氣特性,其Σ埠之電氣響應,在f1’ (2.55 GHz)操作頻率下之輸入返回損耗(|S11|)為20.6 dB,插入損耗(|S21|/|S31|)分別為3.4 dB及3.6 dB,相位差(S21-S31)為-5.3度,隔離度(|S41|)則為23.8 dB,在20-dB返回損耗、20-dB隔離度條件下之百分比頻寬 (fractional bandwidth, FBW)為19.8 % (2.39–2.9 GHz),其振幅不平衡小於 0.7 dB、相位不平衡則小於9度;另在f2’ (5.9 GHz)操作頻率下之輸入返回損耗(|S11|)為12.2 dB,插入損耗(|S21|/|S31|)分別為5.5 dB及5.8 dB,相位差(S21-S31)為-1.6度,隔離度(|S41|)為19.4 dB,在10-dB返回損耗、10-dB隔離度條件下之百分比頻寬為4.2 % (5.87–6.12 GHz),其中振幅不平衡小於 1 dB (5.87–5.97 GHz)、相位不平衡則小於10度(5.87–6.08 GHz)。其Δ埠之電氣響應,在f1’ (2.55 GHz)操作頻率下之輸入返回損耗(|S44|)則為22.8 dB,插入損耗(|S24|/|S34|)分別為3.4 dB及3.7 dB,相位差(S24-S34-180˚)為7.3度,隔離度(|S14|)則為23.8 dB,在20-dB返回損耗、20-dB隔離度條件下之百分比頻寬為18.0 % (2.49 GHz-2.95 GHz),其振幅不平衡小於 0.6 dB、相位不平衡則小於10度;另在f2’ (5.9 GHz)操作頻率下之輸入返回損耗(|S44|)為22.9 dB,插入損耗(|S24|/|S34|)則分別為7.1 dB及6.5 dB,相位差(S24-S34-180˚)為1.9度,隔離度(|S14|)則為19.4 dB,在10-dB返回損耗、10-dB隔離度條件下之百分比頻寬為2.4 % (5.84–6.08 GHz),其中振幅不平衡小於 1 dB (5.84–6.05 GHz)、相位不平衡則小於10度(5.86–5.93 GHz)。另有關諧波抑制的成效,其Σ埠(|S21|/|S31|)及Δ埠(|S24|/|S34|)之電氣響應,在諧波頻率5.1 GHz (2f1’)、7.65 GHz (3f1’)、10.2 GHz (4f1’)、11.8 GHz (2f2’)及12.75 GHz (5f1’)之抑制能力分別達於56.8 dB、37.6 dB、18.1 dB、43.1 dB及45.2 dB以上,除雙頻操作頻段外,其諧波抑制涵蓋範圍為2f1’-5f1’ (含2f2’),其抑制水準至少達18 dB以上。

This work is designed and improved for 180° hybrid coupler, making it to be a circuit with miniaturization, harmonic suppression and dual frequency operation. The stepped impedance unit module is implemented by a complementary-conducting-strip (CCS) transmission line. The unit module is used as a base to replace the 1/4-λg of total length 6/4-λg transmission line, the appropriate proportion of the design to make the circuit miniaturization and dual-band operation, coupled with two-layers open stub to suppress the harmonic.
The CCS TL is used to replace the conventional microstrip line to form the stepped impedance line and the open stub by extracting the CCS TL electrical parameters under different specifications, and this unit module is used to replace the microstrip 1/4-λg transmission line of the ring-shaped 180° hybrid. The six unit modules are connected in cascade to form a full-length 6/4-λg miniaturized, dual-band (2.45/5.8-GHz) 180° hybrid with harmonic suppression.
The results show that the proposed circuit occupied area (excluding I / O PADs) (= 1.5√3  a2, a = 7.3 mm) is only 138.41 mm2. The occupied area of proposed circuit to the traditional ring-shaped rat-race (excluding I/O PADs) (= π × b2, the radius b is 18.44 mm) is only 13%, and the area reduction factor(ARF) is up to 87 %.
The optimum frequency is shifted about 0.1 GHz from f1/f2 (2.45/5.8-GHz) to f1'/f2'(2.55/5.9-GHz) by the measurement results of the prototype circuit of the 180 ° hybrid. Through the implementation shows that the circuit has dual-band operation (f1'/f2', 2.55/5.9-GHz) and harmonic suppression characteristics. For the electrical characteristics of the dual-band operation, the electrical response of the Σ port is 20.6 dB for the input return loss (|S11|) at the operating frequency of f1'(2.55 GHz), and the insertion loss (|S21|/|S31|)is 3.4 dB and 3.6 dB, the phase difference (S21-S31) is -5.3 degrees, and the isolation (|S41|) is 23.8 dB, at 20-dB return loss, 20-dB isolation of the fractional bandwidth (FBW) is 19.8% (2.39–2.9 GHz), the amplitude imbalance is less than 0.7 dB, the phase difference is less than 9 degrees; the other operating frequency at f2'(5.9 GHz), the input return loss (|S11|) is 12.2 dB, the insertion loss (|S21|/|S31|) is 5.5 dB and 5.8 dB, the phase difference (S21-S31) is -1.6 degrees, and the isolation (|S41|) is 19.4 dB . At 10-dB return loss, 10-dB isolation of the FBW is 4.2% (5.87–6.12 GHz), where the amplitude imbalance is less than 1 dB (5.87–5.97 GHz) and the phase difference is less than 10 degrees (5.87–6.08 GHz).The electrical response of the Δ port is 22.8 dB for the input return loss (|S44|) at the operating frequency of f1'(2.55 GHz), the insertion loss (|S24|/|S34|) is 3.4 dB and 3.7 dB, the phase difference is 7.3 degrees, the isolation (|S14|) is 19.4 dB, and the FBW at 20-dB return loss, 20-dB isolation is 18.0% (2.49 GHz-2.95 GHz), the amplitude imbalance is less than 0.6 dB, the phase difference is less than 10 degrees; the input return loss (|S44|) at the operating frequency of f2'(5.9 GHz) is 22.9 dB, the insertion loss (|S24|/|S34|) is 7.1 dB and 6.5 dB, respectively, the phase difference (S24-S34-180°) is 1.9 degrees, and the isolation (|S14|) is 19.4 dB . At 10-dB return loss, 10-dB isolation of the FBW is 2.4% (5.84–6.08 GHz), where the amplitude imbalance is less than 1 dB (5.84–6.05 GHz) and the phase difference is less than 10 degrees (5.86–5.93 GHz). In addition, the electrical response of the harmonic suppression, the electrical response of the Σ port (|S21|/|S31|) and the Δ port (|S24|/|S34|) at the harmonic frequency of 5.1 GHz (2f1'), 7.65 GHz (3f1'), 10.2 GHz (4f1'), 11.8 GHz (2f2') and 12.75 GHz (5f1'), respectively, with the ability of 56.8 dB, 37.6 dB, 18.1 dB, 43.1 dB and 45.2 dB, the harmonic suppression level is at least 18 dB in the range of 2f1'-5f1'(including 2f2').

摘要 i
Abstract iv
誌謝 vii
目錄 viii
圖目錄 xi
表目錄 xvii
論文縮寫及符號對照表 xix
第一章 緒論 1
1.1研究背景及動機 1
1.2研究目的及方法 6
1.3 本文架構 7
第二章 分合波器設計理論及建構 8
2.1 設計流程 8
2.2 180˚分合波器設計原理 11
2.2.1具開路殘段之步階式阻抗180˚分合波器 12
2.3開路殘段介紹 14
2.3.1開路殘段分析與選擇 14
2.3.2小結 18
2.4雙頻及諧波抑制之單元模組建構 19
2.4.1 單元模組參數分析 20
2.4.2單元模組定性定量分析 38
2.5具開路殘段之步階式阻抗單元模組 45
2.6電路模擬驗證 47
第三章 CCS模組建構 51
3.1 CCS 波導結構介紹 51
3.2 CCS波導特性分析 53
3.3雙層開路殘段 65
3.3.1 波導特性分析比較 66
3.3.2 單層開路殘段應用分析 71
3.3.3 雙層開路殘段應用 74
第四章 模擬結果與驗證 80
4.1 模擬布局 80
4.2 模擬結果 83
4.3 實作量測驗證 90
4.4 誤差分析 101
第五章 未來展望 104
5.1 結論 104
5.2未來規劃 105
參考文獻 106


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